OLED Pixel Circuit Timing to Reduce Slanted Line Crosstalk
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Solution Overview
Problem
OLED display devices experience slanted line crosstalk along a diagonal direction due to coupling between gate and data signals, leading to image distortion and reduced display quality.
Innovation Solution
The display device adjusts the timing of gate signals to minimize slanted line crosstalk by ensuring the rising timing of the gate1 signal occurs after the odd gate2 signal, using a timing controlling circuit, data and gate driving circuits, and a display panel with specific signal generation and application protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate signals are applied simultaneously to reduce manufacturing complexity, then device complexity is reduced, but slanted line crosstalk occurs due to coupling between gate and data signals
Solution Approach 1:
The patent applies preliminary action by adjusting the gate signal timing in advance to occur after the data signal is fully saturated. This timing adjustment prevents coupling between gate and data signals before they interact, thereby eliminating slanted line crosstalk while maintaining straightforward simultaneous signal application
2Object-affected harmful factors
If gate signal timing is adjusted to occur after data signal saturation to eliminate crosstalk, then slanted line crosstalk is reduced, but signal timing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the timing parameter of the gate signal to occur after data signal saturation. This single parameter adjustment effectively reduces signal distortion and eliminates slanted line crosstalk without requiring complex control mechanisms
Data Source
AI summary
A display device comprising a storage capacitor connected to a high level voltage line, a first transistor switched according to a voltage of a first capacitor electrode of the storage capacitor, a second transistor switched according to a gate2 signal and connected to a data signal and the first transistor, a third transistor switched according to a gate1 signal and connected to the storage capacitor and the first transistor, a fourth transistor switched according to the gate1 signal and connected to the storage capacitor and an initial voltage, a fifth transistor switched according to an emission signal and connected to the high level voltage and the first transistor, a sixth transistor switched according to the emission signal and connected to the first transistor, and a light emitting diode connected between the sixth transistor and a low level voltage line.