OLED Pixel Circuit Layout for Driving Transistor Stability

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Solution Overview

Problem

Current OLED display substrates face challenges in optimizing the layout of pixel circuits to enhance the length-width ratio of channel regions in driving transistors, which affects current leakage and stability, and in minimizing the impact of power voltage on channel regions.

Innovation Solution

The display substrate incorporates a pixel circuit design with a driving transistor featuring a strip-shaped channel region extending along the second direction, a storage capacitor with a non-overlapping electrode configuration to avoid channel region influence, and a compensation transistor structure to stabilize the gate electrode, all integrated on a base substrate with optimized signal line and power line arrangements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the channel region of the driving transistor is extended to increase the length-width ratio, then current leakage is reduced and stability is improved, but the pixel circuit area increases

Engineering Contradiction:
Improvestability of driving transistorVSAvoidpixel circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The channel region is configured in a strip shape extending along the second direction (vertical direction in the pixel circuit layout), perpendicular to the gate electrode arrangement direction. This dimensional reorientation allows the channel length to increase without proportionally increasing the horizontal footprint, thereby improving the length-width ratio and reducing current leakage while maintaining compact pixel area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The storage capacitor is positioned with its second electrode plate overlapping the first electrode plate in the vertical direction, and the capacitor structure is nested within the pixel circuit boundary. The electrode plates are arranged such that the second electrode plate's orthographic projection overlaps with the first electrode plate's projection, allowing the capacitor to be compactly integrated without significantly increasing the pixel area while maintaining sufficient capacitance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Device complexity

If power voltage lines are routed close to the channel region for compact layout, then device complexity is reduced, but the channel region is affected by power voltage interference

Engineering Contradiction:
Improvesignal line arrangementVSAvoidpower voltage interference on channel region
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The second electrode plate of the storage capacitor is extracted from overlapping with the channel region's orthographic projection, separating the capacitor structure from the transistor's sensitive active area. This spatial extraction eliminates the harmful interaction between the power voltage on the second electrode plate and the channel region, preventing voltage interference while maintaining compact capacitor integration.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The storage capacitor utilizes vertical stacking with overlapping electrode plates in the thickness direction, allowing the capacitor to achieve sufficient capacitance through vertical dimension rather than horizontal expansion. This enables the capacitor to be positioned without interfering with the channel region's horizontal footprint, reducing power voltage interference while maintaining compact layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240420637A1Display substrate and display device
Publication Date: 2024.12.19 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US20240420637A1 patent drawing
  • US20240420637A1 patent drawing
  • US20240420637A1 patent drawing

AI summary

A display substrate and a display device are provided. In the display substrate, the driving transistor includes an active pattern and a gate electrode, the active pattern includes a channel region, and an orthographic projection of the channel region on the base substrate at least partially overlaps with an orthographic projection of the gate electrode on the base substrate; the storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate is electrically connected with the gate electrode of the driving transistor; an orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate on the base substrate, and does not overlap with an orthographic projection of the channel region of the driving transistor on the base substrate.