OLED Pixel Circuit Voltage Biasing for Image Retention Mitigation
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Solution Overview
Problem
OLED displays experience image retention due to a hysteresis effect in pixel transistors, causing noticeable optical artifacts that affect the visibility of on-screen content, especially when displaying images for extended durations or at high luminosities.
Innovation Solution
A pixel array with a first transistor receiving a biasing signal to apply a bias voltage to a second transistor, neutralizing voltage stress and reducing hysteresis effects by initializing the electrical voltage of the second transistor's source terminal during display-frame periods, thereby mitigating image retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If OLED displays are used for extended durations or at high luminosities, then the display can maintain high brightness and visibility, but image retention artifacts occur due to hysteresis effects in pixel transistors
Solution Approach 1:
The patent applies preliminary anti-action by introducing a biasing signal to the first transistor that preemptively counteracts the hysteresis effect before it causes image retention. The biasing signal adjusts the voltage at the source terminal of the second transistor during non-display periods, preparing the transistor to minimize voltage stress and prevent artifact formation when high brightness is subsequently activated.
Solution Approach 2:
The patent employs parameter changes by dynamically modifying the voltage parameters of the pixel circuit transistors. The biasing signal changes the voltage at the source terminal of the second transistor, altering its electrical characteristics to reduce hysteresis. This parameter adjustment allows the transistor to operate in a regime that minimizes image retention while maintaining the ability to achieve high brightness when needed.
2Object-affected harmful factors
If a biasing signal is applied to reduce hysteresis effects, then image retention is mitigated, but the device complexity increases due to additional transistors and control circuits
Solution Approach 1:
The patent applies universality by designing the first transistor to serve multiple functions: it acts as a regular switching transistor for display operation and simultaneously functions as a biasing control element to reduce hysteresis. The biasing signal line is integrated into the existing pixel circuit architecture, allowing the same structural elements to perform both display control and artifact mitigation without requiring entirely separate dedicated components.
Solution Approach 2:
The patent merges the biasing function with the existing transistor structure by coupling the biasing signal to the gate of the first transistor, which then modulates the source voltage of the second transistor. This integration combines the artifact reduction mechanism with the regular pixel circuit operation, eliminating the need for completely separate biasing circuitry and reducing overall device complexity.
Data Source
AI summary
This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.