Pixel Driving Circuit Wiring Layout for Stable OLED Brightness

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Solution Overview

Problem

In OLED displays, parasitic capacitances between data signal lines and the gate or source of driving transistors cause uneven local brightness due to differing voltage jump amplitudes, leading to crosstalk issues.

Innovation Solution

The pixel driving circuit design adjusts the wiring layout by increasing the distance between data signal lines and the gate of the driving transistor, reducing coupling, and optimizing the positioning of power and scan signal lines to stabilize voltage differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the data signal line is positioned close to the gate of the driving transistor, then the wiring complexity is reduced, but parasitic capacitance increases causing voltage jump differences and crosstalk

Engineering Contradiction:
Improvewiring layout complexityVSAvoidparasitic capacitance coupling
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating different spatial relationships for different signal lines relative to the driving transistor gate. The data signal line is positioned at a first distance from the gate, while the power signal line is positioned at a second distance from the gate, with the first distance being greater than the second distance. This localized differentiation in positioning optimizes the balance between wiring complexity and parasitic capacitance coupling for each signal type.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If the distance between data signal line and driving transistor gate is increased, then parasitic capacitance coupling is reduced, but the area occupied by the pixel circuit increases

Engineering Contradiction:
Improvecrosstalk between signal linesVSAvoidpixel circuit area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent utilizes multi-layer wiring architecture to resolve the area constraint. By positioning signal lines on different layers (first signal line on a first layer, second signal line on a second layer), the patent reduces in-plane distance requirements while minimizing pixel circuit area expansion. This dimensional transition from 2D planar layout to 3D stacked layout enables closer positioning without increasing parasitic capacitance coupling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves brightness stability and reduces crosstalk by minimizing the degree of coupling between signal lines and the transistor, enhancing display quality.

Implementation Method 1

parasitic capacitances between data signal lines and the gate or source of driving transistors cause uneven local brightness

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS20260068469A1Wiring structure of pixel driving circuit, display panel, and display device
Publication Date: 2026.03.05 BOE TECHNOLOGY GROUP CO LTD
  • US20260068469A1 patent drawing
  • US20260068469A1 patent drawing
  • US20260068469A1 patent drawing

AI summary

Provided are a wiring structure of a pixel driving circuit, a display panel, and a display device. The wire layout includes: a first switching element, a second switching element and a driving transistor. A source electrode of the driving transistor is connected to a power signal line. The power signal line includes a first power signal line that is in a same direction as a data signal line, and the data signal line is arranged at a position of the first power signal line away from a gate electrode of the driving transistor.