OLED Pixel Layout Power Line Extraction

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Solution Overview

Problem

The existing organic electroluminescence display devices face issues with brightness and uniformity due to increased contact resistance between power lines and thin film transistors, caused by etching processes, which also reduce the effective pixel area and design space for TFTs.

Innovation Solution

The solution involves rearranging the layout of data and gate lines to eliminate the need for power lines within pixel regions, using connecting lines to connect thin film transistors across pixel lines, thereby reducing voltage drops and increasing the effective area for current supply and capacitor size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power lines are formed in pixel regions and gate insulating layer is etched to connect power lines with driving TFTs, then electrical connection is achieved, but contact resistance increases and brightness uniformity degrades

Engineering Contradiction:
Improveelectrical connectionVSAvoidbrightness uniformity
Core Design Contradiction:
ReliabilityVSIllumination intensity

Solution Approach 1:

The power lines are extracted from the pixel regions and relocated to the non-pixel region. This removes the harmful etching process from within pixel regions, eliminating the source of contact resistance and brightness non-uniformity while maintaining the necessary electrical connections through alternative routing paths.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The power line routing is changed from a planar arrangement within pixel regions to a three-dimensional arrangement that utilizes the non-pixel region and extends through multiple layers. This dimensional change allows electrical connections to be achieved without etching through the gate insulating layer in pixel regions, thereby avoiding contact resistance issues.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If power lines are formed in pixel regions, then electrical connection is provided, but effective pixel area is reduced

Engineering Contradiction:
Improveelectrical connectionVSAvoideffective pixel area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The power lines are extracted from the pixel regions and relocated to the non-pixel region. This extraction removes the occupation of pixel area by power lines, thereby maximizing the effective pixel area available for light-emitting elements and improving overall display area utilization.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If conventional fabrication process is used, then manufacturing is simple, but yield is limited by OLED fabrication process

Engineering Contradiction:
Improvefabrication process simplicityVSAvoiddevice yield
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The display device is segmented into a pixel region and a non-pixel region, with different functional elements placed in each. The power lines are specifically routed through the non-pixel region, separating the power distribution function from the pixel array fabrication process. This segmentation allows the power line connections to be made without relying on the OLED fabrication yield, thereby improving overall device yield.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7671530B2Organic electroluminescence display device and method of fabricating the same
Publication Date: 2010.03.02 LG DISPLAY CO LTD
  • US7671530B2 patent drawing
  • US7671530B2 patent drawing
  • US7671530B2 patent drawing

AI summary

Provided are an organic electroluminescence display device and method of fabricating the same. An organic electroluminescence display device according to the present invention includes a first substrate; a plurality of data lines arranged in a first direction on the first substrate; a plurality of gate lines arranged in a second direction on the first substrate; a plurality of pixel regions defined by the gate lines and the data lines, wherein a first pixel line is defined as a line of the pixel regions arranged in the first direction and a second pixel line is defined as a line of the pixel regions arranged in the second direction; a thin film transistor in each pixel region; a plurality of first connecting lines electrically connecting the thin film transistors of the first pixel lines with each other; and a second connecting line electrically connecting the thin film transistor of at least one of the second pixel lines.