OLED Array Substrate Power Wire Layer Resistance Reduction
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Solution Overview
Problem
Conventional OLED displays face issues with non-uniform brightness due to high resistance in the power wire layer, leading to voltage drops and mura phenomena in large-sized displays, which reduce efficiency and aperture ratio.
Innovation Solution
The array substrate features a power wire layer arranged separately and in a lattice-like structure, connected to the source layer via via holes, increasing the conductive cross-sectional area and reducing resistance, while overlapping with gate and drain layers to minimize area occupation and enhance aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the power wire layer is arranged in the same layer as gate or source/drain layers in conventional OLED displays, then the manufacturing process is simplified, but the resistance of the power wire layer increases and aperture ratio decreases
Solution Approach 1:
The patent transitions the power wire layer from a planar arrangement (same layer as gate/source/drain) to a three-dimensional stacked arrangement (separate layer below or above), thereby reducing in-plane resistance while optimizing aperture ratio. This dimensional change allows the power wire to extend across the entire pixel area without occupying display area.
2Device complexity
If the power wire layer is arranged in the same layer as gate or source/drain layers, then device complexity is reduced, but the conductive cross-sectional area is limited and resistance increases
Solution Approach 1:
By moving the power wire layer to a separate layer in the vertical dimension, the patent enables the power wire to span the entire pixel area (increasing conductive cross-sectional area) without adding horizontal complexity. The stacked configuration allows broader power distribution paths.
3Reliability
If the power wire layer occupies a large area in the same layer as gate/source/drain layers, then connectivity is improved, but aperture ratio decreases
Solution Approach 1:
The patent resolves this contradiction by placing the power wire layer in a separate vertical layer, allowing it to extend across the full pixel area for optimal connectivity while not occupying horizontal display area. This enables the power wire to maintain excellent connectivity without compromising aperture ratio.
4Ease of manufacture
If conventional power wire arrangement is used, then manufacturing is easier, but voltage drop occurs and mura phenomena appear in large-sized displays
Solution Approach 1:
By transitioning to a stacked layer configuration, the patent reduces power wire resistance through increased conductive cross-sectional area and optimized current distribution paths. This eliminates voltage drops and mura phenomena in large-sized displays while maintaining manufacturing feasibility through standard semiconductor layering processes.
Data Source
AI summary
The present invention provides an array substrate and a manufacturing method thereof. The array substrate of the present invention comprises multiple pixel units arranged in an array, each pixel unit comprising a substrate, an active layer, a source layer and a drain layer arranged in the same layer, and a gate layer; wherein each pixel unit further comprises a power wire layer connected to the source layer via a via hole. Since the power wire layer of the present invention is separately provided as a layer, the area of the projection of the power wire layer on the substrate may be larger, that is, the conductive cross-sectional area of the power wire layer may be larger, and thus the resistance of the power wire layer is decreased. Therefore, difference among currents of different pixel units is reduced, and thus the mura phenomenon generated in displaying is alleviated.