OLED Power Wiring Layout for Narrow Bezels and Low Touch Noise

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Solution Overview

Problem

Existing flexible organic light-emitting display devices face challenges in reducing the size of the non-display area and minimizing noise interference due to the design of power voltage wirings and touch screen structures.

Innovation Solution

The implementation of asymmetrical power voltage wirings with overlapping layers and asymmetrical structures, along with a fan-out wiring and dam structures, reduces the width of the peripheral area and minimizes noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power voltage wirings are designed with sufficient width to ensure low resistance, then electrical conductivity is improved, but the area of the non-display region increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidnon-display area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a single-plane wiring layout to a multi-layer three-dimensional structure. Power voltage wirings are distributed across different layers (first and second power voltage wirings in different planes), allowing current to flow through multiple parallel paths. This vertical dimensionality change reduces the required width of individual wiring lines while maintaining low overall resistance, thereby reducing the non-display area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power voltage wiring system is segmented into multiple separate wiring layers (first power voltage wiring and second power voltage wiring). Each layer carries a portion of the total current, distributing the electrical load across multiple segments. This segmentation allows each individual wiring line to be narrower while collectively providing sufficient conductivity.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If power voltage wirings are placed close to touch screen structures, then device complexity is reduced, but noise interference increases

Engineering Contradiction:
Improvewiring layout complexityVSAvoidnoise interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent utilizes vertical separation by placing power voltage wirings and touch screen structures in different layers/planes. This three-dimensional arrangement increases the physical distance between noisy power lines and sensitive touch sensing elements without requiring complex lateral routing, thus reducing noise interference while maintaining relatively simple device structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces intermediate structures (such as insulation layers and spacing structures) between the power voltage wirings and touch screen structures. These intermediaries act as barriers that shield the touch sensing elements from electromagnetic noise generated by the power lines, reducing noise interference without significantly increasing device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12628517B2Organic light-emitting display device
Publication Date: 2026.05.12 SAMSUNG DISPLAY CO LTD
  • US12628517B2 patent drawing
  • US12628517B2 patent drawing
  • US12628517B2 patent drawing

AI summary

An organic light-emitting display device includes a base substrate, a pixel array, a first power voltage wiring and a second power voltage wiring. The base substrate includes a pixel area and a peripheral area. The pixel array is disposed in the pixel area. The first power voltage wiring is disposed in the peripheral area and includes a first lower power voltage line and a first upper power voltage line. The first upper power voltage line is disposed on and contacts the first lower power voltage line. The second power voltage wiring is disposed in the peripheral area and includes a second lower power voltage line and a second upper power voltage line. The second upper power voltage line is disposed on and contacts the second lower power voltage line. The first upper power voltage line overlaps the second lower power voltage line in a plan view.