OLED Array Substrate Reset Line Layout for Uniform Brightness
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Solution Overview
Problem
Existing OLED display technologies face challenges in maintaining consistent brightness due to variations in driving current, which can lead to non-uniform illumination across the display panel.
Innovation Solution
The array substrate incorporates a complex network of reset signal lines and transistors, including double-gate transistors and interconnected reset signal supply networks, to provide uniform voltage levels across subpixels, ensuring consistent light emission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple reset signal line configuration is used, then device complexity is reduced, but brightness uniformity deteriorates due to driving current variations
Solution Approach 1:
The reset signal lines are segmented into multiple independent lines (first reset signal lines and second reset signal lines) that separately control different groups of subpixels. This segmentation allows independent optimization of reset signals for different regions, compensating for driving current variations and achieving uniform brightness across the display panel.
Solution Approach 2:
Different reset signal lines provide different reset voltage levels or timing characteristics to different subpixel groups based on their specific driving current characteristics. This local quality adjustment ensures that each subpixel group receives appropriately tailored reset signals to maintain uniform brightness despite variations in driving current.
2Illumination intensity
If multiple reset signal lines with different configurations are used, then brightness uniformity is improved, but device complexity increases
Solution Approach 1:
The multiple reset signal lines share common functional characteristics and control logic, allowing them to be designed using standardized patterns and fabrication processes. This multi-functionality approach enables the system to achieve brightness uniformity through multiple channels while maintaining design efficiency and reducing overall system complexity.
Solution Approach 2:
The reset signal lines are designed to provide equipotential reset voltage levels to corresponding subpixel groups, ensuring that all subpixels receive equivalent reset conditions despite physical layout variations. This equipotentiality principle simplifies the design by establishing consistent voltage references across the display panel.
3Illumination intensity
If uniform voltage levels are provided across all subpixels, then brightness uniformity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The reset signal lines are designed to automatically compensate for voltage level variations through their inherent circuit configuration and timing characteristics. Each reset signal line self-adjusts to provide appropriate voltage levels to its controlled subpixel group, reducing the need for external calibration and high-precision manufacturing controls.
Solution Approach 2:
The system utilizes parameter changes in the reset signal characteristics (such as voltage level, pulse width, or timing) to compensate for manufacturing variations. By dynamically adjusting these parameters based on subpixel group requirements, the system achieves uniform brightness output without requiring extremely tight manufacturing tolerances.
Data Source
AI summary
An array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines, and a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. The respective third reset signal line is connected to source electrodes of second reset transistors in a column of subpixels. A drain electrode of the seventh transistor is connected to an N3 node. The N3 node is a node connected to a drain electrode of the driving transistor and a source electrode of the light emitting control transistor.