OLED Array Substrate Reset Network for Uniform Subpixel Initialization
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Solution Overview
Problem
Current OLED display technologies face challenges in maintaining uniform voltage levels across subpixels, leading to residual image and low-frequency flicker issues due to inefficiencies in reset signal distribution and transistor design.
Innovation Solution
The array substrate incorporates an interconnected reset signal supply network with multiple reset signal lines and lightly doped drain regions in transistors, ensuring uniform initialization and reduced current leakage, which addresses the voltage level inconsistencies and improves display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple reset signal line configuration is used, then device complexity is reduced, but brightness uniformity and driving current consistency deteriorate
Solution Approach 1:
The reset signal lines are segmented into three distinct types (first, second, and third reset signal lines) with different configurations and voltage levels. This segmentation allows each line type to serve specific subpixel groups differently, enabling precise control of reset voltages to achieve uniform brightness across all subpixels while managing device complexity through organized structure.
Solution Approach 2:
Different reset signal lines provide different voltage levels (first reset voltage, second reset voltage, third reset voltage) to different groups of subpixels based on their specific requirements. This local quality approach ensures that each subpixel receives the appropriate reset voltage for its position and characteristics, achieving uniform brightness without requiring a uniformly complex signal distribution network.
2Illumination intensity
If multiple reset signal lines with different voltage levels are used, then brightness consistency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a multi-dimensional reset signal network by adding vertical connections between different reset signal line types. The second reset signal lines connect to third reset signal lines, creating a three-dimensional signal distribution architecture that enables complex voltage control patterns while maintaining organizational structure and manageability.
Solution Approach 2:
The interconnected reset signal network is designed to serve multiple functions simultaneously: first reset signal lines handle row-specific reset operations, second reset signal lines provide column-specific control, and third reset signal lines offer additional voltage levels. This multi-functional design achieves comprehensive brightness control without requiring separate independent signal systems for each function.
3Reliability
If reset transistors with lightly doped drain regions are used, then driving current stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the electrical parameters of the reset transistors by implementing lightly doped drain regions, which changes the doping concentration profile in the transistor structure. This parameter change improves the transistor's electrical characteristics and driving current stability while maintaining compatibility with existing semiconductor fabrication processes, thus balancing reliability improvement with manufacturability.
Data Source
AI summary
An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.