Variable Sampling Time for OELD Display Uniformity

The patent applies dynamics by making the sampling time variable rather than fixed. The sampling time is dynamically adjusted based on the gray level of each pixel, allowing the system to adapt to different threshold voltage and S-factor conditions. This is achieved through a sampling time control unit that selects different sampling time periods according to the measured gray level, thereby resolving the contradiction between device complexity and display uniformity.

The patent changes the parameter of sampling time based on gray level conditions. By categorizing gray levels into different ranges (first gray level range, second gray level range, third gray level range) and assigning different sampling time periods to each range, the system optimizes the sampling process for varying transistor characteristics. This parameter change approach improves display uniformity without requiring complete redesign of the sampling control mechanism.

The patent optimizes the parameter of sampling time by matching it to the gray level range. For low gray levels where S-factor variations are more critical, a longer sampling time period is used to ensure accurate offset voltage sampling and improve display uniformity. For high gray levels where threshold voltage variations dominate, a shorter sampling time period is sufficient, thereby maintaining productivity. This conditional parameter adjustment resolves the contradiction between precision and efficiency.

The patent applies partial action by using extended sampling time only when necessary (for low gray levels), rather than continuously for all pixels. The sampling time control unit selectively applies longer sampling periods based on gray level measurements, avoiding unnecessary time extension for high gray levels where it would not provide additional benefit. This partial application maintains productivity while improving uniformity where needed.