OLED Display Substrate Scan Line Layout for Lower Resistance
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Solution Overview
Problem
Existing display technologies face challenges in optimizing the design of display substrates for OLEDs, particularly in reducing the resistance of scan lines while maintaining the parasitic capacitance, which affects the driving efficiency and layout optimization.
Innovation Solution
The proposed display substrate design includes a semiconductor layer, multiple metal layers, and insulating layers arranged sequentially on the substrate. This design features a scan line with a specific overlapping region and a scan connection line that reduces the resistance of the scan line without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the scan line length is increased to cover more sub-pixels, then the scanning coverage is improved, but the line resistance increases which degrades signal quality
Solution Approach 1:
The scan line is divided into multiple segments (first scan line portion and second scan line portion) that are spatially separated and routed through different metal layers. This segmentation allows each portion to be optimized independently, reducing the effective resistance path while maintaining full coverage.
Solution Approach 2:
The patent utilizes multiple metal layers (first, second, third, and fourth metal layers) to route scan line portions in different vertical dimensions. By transitioning from a single-plane layout to a multi-layer three-dimensional routing approach, the scan lines can achieve better electrical performance without increasing planar footprint.
2Reliability
If the scan line width is increased to reduce resistance, then the electrical conductivity is improved, but the available layout area for other components is reduced
Solution Approach 1:
The patent resolves this contradiction by routing different scan line portions through multiple vertical layers rather than increasing width in the planar domain. The first scan line portion is routed in one metal layer while the second portion is routed in another metal layer, effectively using the vertical dimension to maintain thin line widths while achieving low resistance through optimized current paths.
3Reliability
If the number of metal layers is increased to optimize scan line routing, then the electrical performance is improved, but the manufacturing complexity increases
Solution Approach 1:
The scan line routing is segmented into distinct portions that can be formed in different metal layers using separate patterning and deposition steps. This segmentation allows for modular manufacturing where each layer can be processed independently, making the complex multi-layer structure more manufacturable.
Solution Approach 2:
The patent performs preliminary routing planning where the first scan line portion is routed through earlier metal layers and the second portion through later metal layers. This preliminary action in the design phase optimizes the routing paths before final fabrication, reducing the complexity of alignment and patterning during manufacturing.
Data Source
AI summary
A display substrate, including: a base, and a plurality of sub-pixels arranged on the base. At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit includes a plurality of transistors and at least one storage capacitor. In a direction perpendicular to the base, the display substrate includes: a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, which are sequentially arranged on the base. The semiconductor layer includes: an active layer of the plurality of transistors. The first metal layer includes at least a scanning line extending in a first direction, a gate electrode of the plurality of transistors, and a first capacitor electrode plate of the storage capacitor.