OLED Input Sensor Layout Using Partition Wall Line Patterns
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Solution Overview
Problem
The close proximity between conductive layers in organic light-emitting display panels leads to parasitic capacitance issues in input sensors, affecting their performance.
Innovation Solution
The display device incorporates a partitioning wall with line patterns that minimize overlapping areas between conductive lines and the partitioning wall, using a layered structure with specific materials to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conductive layers are placed close together in the input sensor, then the device structure is compact, but parasitic capacitance increases and sensing performance deteriorates
Solution Approach 1:
An insulating layer is introduced between the conductive lines of the input sensor and the cathode to act as an intermediary that reduces parasitic capacitance. This mediator layer allows the conductive layers to remain in close proximity for compact structure while preventing harmful electrical interaction through its insulating properties.
2Reliability
If the partitioning wall is made with continuous conductive material, then electrical connection is improved, but parasitic capacitance with conductive lines increases
Solution Approach 1:
The partitioning wall is segmented by introducing line patterns that remove portions of the conductive material, dividing it into separate regions. This segmentation maintains electrical connection within each segment while reducing the continuous overlapping area with conductive lines, thereby reducing parasitic capacitance.
Solution Approach 2:
The partitioning wall is designed with non-uniform structure where line patterns create regions of different conductive material presence. Areas where conductive lines pass have reduced conductive material (line patterns), while other areas maintain full conductive connection, optimizing both electrical connection and parasitic capacitance reduction locally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic capacitance, enhancing the performance and sensitivity of the input sensor by minimizing overlapping areas and electrical interference.
Implementation Method 1
parasitic capacitance between, for example, the cathode and conductive lines included in the input sensor may occur
Data Source
AI summary
A display device includes a display panel including a base layer including light-emitting areas and a non-light-emitting area adjacent to the light-emitting areas, a pixel defining layer disposed on the base layer and having openings defined, a partitioning wall disposed on the pixel defining layer, light-emitting elements, each including an anode disposed in a corresponding one of the openings, a cathode contacting the partitioning wall, and a light-emitting pattern disposed between the anode and the cathode, and an encapsulation layer covering the light-emitting elements, and an input sensor disposed on the display panel, the input sensor including conductive lines overlapping the partitioning wall. The partitioning wall may have line patterns defined therein by removing at least a portion of the partitioning wall, with the line patterns overlapping the non-light-emitting area, and at least some of the conductive lines may overlap the line patterns.