OLED Pixel Circuit Shield Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing OLED displays face issues with parasitic capacitance, which lead to increased power consumption and reduced display quality due to overlapping areas between the shield layer and semiconductor layer, causing kickback voltages and RC delays.
Innovation Solution
The OLED display design minimizes the overlap between the shield layer and specific transistors, particularly the switching transistor, by maintaining a gap and using a shield layer configuration that includes extended and expanded portions to receive driving voltage, thereby reducing parasitic capacitance and stabilizing transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the shield layer overlaps the semiconductor layer to provide shielding, then electromagnetic interference is reduced, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The shield layer is designed with non-uniform coverage, providing shielding only in specific regions where electromagnetic interference occurs (overlapping with the third transistor and connection portion) while avoiding overlap with the second transistor. This local化的 shielding approach reduces parasitic capacitance in critical areas without compromising overall electromagnetic interference protection.
Solution Approach 2:
The shield layer is segmented into distinct regions with different functions: an overlapped portion that provides shielding for the third transistor and connection portion, and a non-overlapping portion that avoids the second transistor. This segmentation allows the shield layer to perform shielding functions while minimizing parasitic capacitance formation.
2Object-affected harmful factors
If the shield layer overlaps the semiconductor layer to provide shielding, then electromagnetic interference is reduced, but display quality deteriorates due to kickback voltages
Solution Approach 1:
The shield layer provides localized shielding coverage that targets specific areas prone to electromagnetic interference (the third transistor and connection portion) while deliberately avoiding overlap with the second transistor. This selective approach prevents kickback voltages that would degrade display quality while maintaining necessary electromagnetic interference protection.
Solution Approach 2:
The design converts the potential harm of the shield layer causing parasitic capacitance into a benefit by strategically positioning the shield layer to overlap only with the third transistor and connection portion. This creates a scenario where the shield layer provides electromagnetic interference protection without the harmful side effect of increasing parasitic capacitance, thereby improving display quality.
3Object-affected harmful factors
If the shield layer is positioned close to signal lines for effective shielding, then electromagnetic interference is reduced, but RC delays increase
Solution Approach 1:
The shield layer is positioned close to the third transistor and connection portion to provide effective electromagnetic interference shielding, while maintaining a gap from the first and second signal lines. This localized positioning enables the shield layer to reduce electromagnetic interference without creating significant parasitic capacitance that would cause RC delays.
Data Source
AI summary
An organic light emitting diode (“OLED”) display includes a semiconductor layer on a substrate, first and second signal lines on the semiconductor layer, a shield layer on the first and second signal lines, a data line on the shield layer, and an OLED on the data line, where the transistor includes a driving transistor, a second transistor connected to the first signal line and the data line, and a third transistor including a gate electrode connected to the first signal line, a third electrode connected to a second electrode of the driving transistor, and a fourth electrode connected to a gate electrode of the driving transistor, the shield layer includes an overlapped portion overlapping at least a part of the connection portion and non-overlaps the second transistor, and the shield layer is separated from the first and second signal lines with a gap therebetween in a plan view.