Integrated Shift Register for OLED Blanking and Scan Output

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Solution Overview

Problem

The existing OLED gate driving circuits are complex and inefficient, leading to increased chip area and difficulty in achieving high resolution and narrow bezel designs.

Innovation Solution

A shift register is introduced that integrates the functions of the sense unit, scan unit, and connection unit into a single circuit, utilizing a first and second input sub-circuit to control output signals during display and blanking periods, respectively, and includes a shared output sub-circuit to reduce circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the gate driving circuit is formed by a combination of three sub-circuits (sense unit, scan unit, and connection unit), then the circuit can output a complex pulse, but the circuit structure becomes very complicated and the chip area increases

Engineering Contradiction:
Improvecircuit structureVSAvoidchip area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent merges the sense unit, scan unit, and connection unit into a single integrated shift register circuit. The circuit uses shared components including a single output transistor, capacitors, and control nodes that serve multiple functions simultaneously, thereby reducing the overall chip area while maintaining the ability to generate complex output pulses required for OLED display driving.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit design implements multi-functionality where the same circuit blocks and components perform multiple roles. For example, the output sub-circuit handles both sensing and scanning operations, and control nodes are reused across different operational phases (display period and blanking period), eliminating the need for separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If the gate driving circuit is integrated into the display, then the chip area is reduced, but the circuit must handle both display and blanking periods with independent control

Engineering Contradiction:
Improvechip areaVSAvoidcontrol mechanism
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the frame period into distinct display period and blanking period operations. During the display period, the circuit responds to display input signals to output display signals. During the blanking period, the circuit responds to blanking input signals to output blanking signals. This temporal segmentation allows independent control of each period while using the same physical circuit, reducing area without requiring separate circuits for each function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit implements dynamic switching between different operational modes based on the current period. The control nodes and transistors are dynamically activated or deactivated depending on whether the circuit is in display period or blanking period, allowing the same hardware to adapt its behavior to different operational requirements without physical reconfiguration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12518671B2Shift register, gate driving circuit, display apparatus and driving method
Publication Date: 2026.01.06 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US12518671B2 patent drawing
  • US12518671B2 patent drawing
  • US12518671B2 patent drawing

AI summary

Disclosed is a shift register (200) including a first input sub-circuit (210), configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node (Q) in a blanking period of time of a frame; a second input sub-circuit (220), configured to receive a second input signal from a second input terminal and output a display output control signal to the first node (Q) in a display period of time of the frame; an output sub-circuit (230), configured to output a composite output signal via an output terminal (OUT) under control of the first node (Q), the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.