OLED Storage Capacitor via Stacked Gate Electrodes
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Solution Overview
Problem
High-resolution OLED displays face challenges in securing sufficient capacitance due to increased sensitivity to wire width variations, contact hole size, and alignment errors, which affect the performance of storage capacitors.
Innovation Solution
The OLED display structure includes a substrate with a semiconductor driving channel, multiple gate electrodes, and an interlayer insulating layer with contact holes to electrically connect the gate electrodes, forming a storage capacitor with increased capacitance by using a larger second driving gate electrode and the driving voltage line as storage electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If resolution is increased, then display quality is improved, but pixel size decreases resulting in smaller margin for error in processing steps
Solution Approach 1:
The gate electrode is divided into two separate gate electrodes (first gate electrode and second gate electrode) positioned at different heights. This segmentation allows each gate electrode to be formed with relaxed dimensional tolerances while collectively providing the required electrical function and capacitance, thereby resolving the contradiction between high resolution and manufacturing precision.
Solution Approach 2:
The invention introduces a vertical dimension by forming the second gate electrode above the first gate electrode at different heights. This three-dimensional arrangement increases the effective capacitance area without expanding the planar pixel footprint, thus maintaining high resolution while compensating for manufacturing variations in wire widths and contact hole sizes.
2Measurement precision
If pixel size is reduced for higher resolution, then display detail is improved, but storage capacitor capacitance becomes insufficient
Solution Approach 1:
By stacking gate electrodes vertically at different heights, the invention increases the effective capacitance area in the vertical dimension. This allows sufficient capacitance to be achieved within the reduced pixel area required for high resolution displays, resolving the contradiction between pixel size reduction and capacitance maintenance.
Solution Approach 2:
The multi-layer gate electrode structure serves dual functions: it provides the necessary gate control voltage application to the semiconductor channel while simultaneously functioning as the storage capacitor electrodes. This multi-functionality eliminates the need for separate dedicated capacitor structures, enabling sufficient capacitance within the constrained pixel area.
3Measurement precision
If wire widths are reduced for higher resolution, then pixel density is improved, but wire width variations and alignment errors increase
Solution Approach 1:
The gate control function is segmented into two vertically stacked gate electrodes rather than relying on a single thin wire. This segmentation reduces the criticality of precise lateral alignment and width control, as the vertical stacking provides additional electrical connection paths and tolerance for dimensional variations in the interconnect structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitance of storage capacitors in high-resolution OLED displays, improving their performance and reliability by mitigating the effects of manufacturing errors and increasing the area for gate voltage application.
Implementation Method 1
Light is emitted by combining electrons injected from a cathode, which is one electrode, with holes injected from an anode, which is the other electrode, in the organic emission layer to generate excitons, allowing the excitons to release energy.
Data Source
AI summary
An organic light-emitting diode display is disclosed. In one aspect, the display includes a semiconductor layer including a driving channel, a first gate insulating layer at least partially covering the semiconductor layer, and a first driving gate electrode formed over the first gate insulating layer and overlapping the driving. A second gate insulating layer at least partially covers the first driving gate electrode. The display also includes a second driving gate electrode formed over the second gate insulating layer and overlapping the first driving gate electrode, an interlayer insulating layer at least partially covering the second driving gate electrode, a driving voltage line formed over the interlayer insulating layer and overlapping the second driving gate electrode, and a connector formed over the interlayer insulating layer and connected to the first and second driving gate electrodes.