OLED Display Substrate Active-Layer Layout for High Resolution
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Solution Overview
Problem
Existing display technologies face challenges in achieving high resolution while maintaining high light transmittance and reducing manufacturing costs, particularly in organic light-emitting diode (OLED) display panels.
Innovation Solution
A display substrate design with integrated active layers and optimized wiring configurations, including power supply and data lines, reduces the width of active connection portions and minimizes overlap with metal wirings, enhancing light transmittance and allowing for higher pixel density without increasing manufacturing complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the resolution of OLED display panel is increased, then the pixel density is improved, but the light transmittance deteriorates due to increased wiring and active layer overlap
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked arrangement of transistors across multiple layers (first, second, and third layers). This vertical stacking allows pixel circuits to be arranged in the thickness direction, reducing the horizontal footprint and enabling higher pixel density without proportionally increasing the area occupied by wirings and active layers, thereby maintaining light transmittance.
Solution Approach 2:
The pixel circuit is divided into multiple independent transistor components distributed across different layers. Each layer contains specific transistors (e.g., first layer has first transistor, second layer has second transistor), allowing functional segmentation that reduces inter-layer interference and optimizes the arrangement of active layers and wirings to minimize overlap.
2Manufacturing precision
If more pixel units are arranged in limited space, then the resolution is improved, but the manufacturing complexity increases due to more wiring connections
Solution Approach 1:
By arranging transistors in multiple stacked layers, the patent reduces the number of wirings required in the planar direction. Connections between layers are established through vertical conductive structures, reducing the overall wiring complexity compared to increasing pixel density in a single layer.
Solution Approach 2:
Multiple transistor functions are combined within a shared pixel unit structure across layers. The pixel circuit integrates multiple transistors that work together to control single or multiple light emitting elements, reducing the total number of independent wiring connections needed compared to having separate circuits for each element.
3Reliability
If the active layers are arranged to cover more area for better transistor performance, then the device functionality is improved, but the light transmittance deteriorates due to increased overlap with metal wirings
Solution Approach 1:
Transistors are distributed across multiple vertical layers, allowing active layers to be positioned at different heights. This three-dimensional arrangement reduces the planar overlap between active layers and metal wirings, as wirings can be routed in spaces between layers or at different vertical positions, maintaining transistor performance while improving light transmittance.
Solution Approach 2:
Different regions of the display panel have optimized wiring and active layer arrangements based on local requirements. In regions where light transmittance is critical, the arrangement minimizes overlap, while in regions where transistor performance is prioritized, the active layers are adequately sized and positioned.
Data Source
AI summary
A display substrate, including a base substrate, and a driving circuit layer and light emitting elements formed on the base substrate, and in a same pixel circuit, an active general layer includes a first column-wise active portion including active layers of a data writing transistor and a first light emission control transistor, and a first active connection portion, an orthographic projection of the first active connection portion on the base substrate at least partially overlapping an orthographic projection of a corresponding power supply line on the base substrate, a dimension of the first active connection portion in a row direction of the pixel units less than a dimension of the active layer of the data writing transistor in the row direction, and a dimension of the active layer of the first light emission control transistor in the row direction. A display panel is further provided.