OLED Substrate Bending Control via Selective Insulating Layer Removal
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Solution Overview
Problem
High-temperature annealing processes during polycrystalline silicon layer crystallization can cause insulating layers to shrink and substrates to bend, leading to device failures in OLED display devices.
Innovation Solution
A method is developed where parts of the insulating layers, such as the buffer layer, gate insulating layer, or interlayer insulating layer, on the non-pixel region of the substrate are selectively removed, reducing the substrate's bending by 8% to 40% of the panel area, thereby preventing substrate deformation during the annealing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing process is used for polycrystalline silicon layer crystallization, then crystallization quality is improved, but substrate bending and insulating layer shrinkage occur
Solution Approach 1:
The substrate is divided into pixel regions and non-pixel regions. The insulating layer is selectively removed only from the non-pixel regions, allowing differential thermal behavior between regions during annealing. This segmentation enables the crystallization process to proceed without causing substrate bending, as the removed insulating layer from non-pixel regions prevents uniform shrinkage across the entire substrate.
2Shape
If insulating layer is removed from non-pixel region, then substrate bending is prevented, but manufacturing process complexity increases
Solution Approach 1:
The insulating layer is removed from the non-pixel regions before the high-temperature annealing process. This preliminary action prepares the substrate to withstand the thermal stress of crystallization without bending, as the insulating layer removal is completed in advance to prevent shrinkage during the subsequent annealing step.
3Temperature
If metal catalyst is used for polycrystalline silicon formation, then crystallization temperature is reduced, but metal contamination deteriorates device characteristics
Solution Approach 1:
The metal catalyst layer is completely removed after the crystallization process. The metal catalyst is temporarily introduced to enable low-temperature crystallization, then extracted in the form of nanoparticles that are subsequently removed through etching processes. This extraction eliminates metal contamination while retaining the benefit of reduced crystallization temperature.
Solution Approach 2:
The metal catalyst serves as an intermediary substance that facilitates the crystallization process at lower temperatures. It mediates between the amorphous silicon layer and the desired polycrystalline structure, enabling crystallization without direct high-temperature exposure. After serving its purpose, the metal catalyst is removed, leaving no contamination in the final device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces substrate bending and prevents damage by allowing the substrate to maintain its shape, ensuring the integrity and functionality of the OLED display device during manufacturing.
Implementation Method 1
the metal catalyst is diffused to the polycrystalline silicon layer through the capping layer by means of an annealing process or laser to form a seed
Implementation Method 2
an annealing process is performed to crystallize
Implementation Method 3
a high-temperature heat treatment
Implementation Method 4
irradiation with a laser
Implementation Method 5
this may cause an insulating layer formed of the same size as a substrate to shrink, and the substrate may be bent
Data Source
AI summary
An organic light emission diode (OLED) display device and a method of fabricating the same, wherein the OLED display device includes a substrate including a pixel region and a non-pixel region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, and including a channel region and source/drain regions, a gate electrode disposed to correspond to the channel region of the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, source/drain electrodes electrically connected to the source/drain regions of the semiconductor layer, and an interlayer insulating layer insulating the gate electrode from the source/drain electrodes, wherein areas of the buffer layer, the gate insulating layer and the interlayer insulating layer that are on the non-pixel region, respectively, are removed, and the partially removed area is 8% to 40% of a panel area.