OLED Display Substrate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In the field of OLED displays, the increasing pixel density and compact layout of high-resolution displays lead to increased signal line resistance and parasitic capacitance, causing signal delay, voltage drop, and reduced display quality due to the higher requirements for structural design of display substrates.
Innovation Solution
A display substrate design featuring a base substrate with sub-pixels arranged in rows and columns, incorporating a pixel circuit with driving, data writing, compensation, and storage sub-circuits, along with a power line and electrical connection layer, optimized to reduce signal line resistance and capacitance by precise arrangement and connection of signal lines and electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to achieve high-resolution display, then display quality is improved, but signal line resistance and parasitic capacitance increase causing signal delay and voltage drop
Solution Approach 1:
The patent introduces a dual-layer via hole structure (first via hole and second via hole at different depths) to connect signal lines across multiple layers. This three-dimensional routing approach allows signal lines to be distributed in the vertical dimension, reducing parasitic capacitance between adjacent lines while maintaining high pixel density in the horizontal plane.
Solution Approach 2:
The via hole connection structure is segmented into multiple sections (first via hole connecting first to second conductive layers, second via hole connecting second to third conductive layers). This segmentation distributes the electrical connection across multiple interfaces, reducing the parasitic capacitance at any single interface and improving signal integrity.
2Productivity
If pixel circuits are compactly arranged to increase pixel density, then display resolution is improved, but parasitic capacitance increases causing signal delay
Solution Approach 1:
By routing connections through multiple vertical layers via stacked via holes, the patent separates signal paths in the vertical dimension. This allows compact horizontal arrangement of pixel circuits while maintaining adequate electrical isolation, thereby reducing parasitic capacitance and signal delay despite high pixel density.
Solution Approach 2:
The second conductive layer and second via hole act as intermediaries between the first and third conductive layers. This intermediate structure provides additional spacing and isolation between signal lines, reducing parasitic capacitance effects while enabling compact pixel circuit arrangement.
3Reliability
If signal lines are arranged to reduce resistance, then voltage drop is reduced, but device complexity increases due to additional power lines and connection layers
Solution Approach 1:
The second conductive layer serves multiple functions: it provides electrical connection between first and third conductive layers via second via holes, acts as an additional power distribution network, and provides mechanical support. This multi-functionality reduces the need for separate dedicated structures, managing complexity while improving voltage stability.
Solution Approach 2:
The patent merges the power distribution function into the existing multi-layer conductive structure. The first, second, and third conductive layers collectively serve both signal transmission and power distribution roles, eliminating the need for separate power line structures and reducing overall device complexity.
Data Source
AI summary
A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, a first power line and an electrical connection layer on the base substrate. Each sub-pixel includes a pixel circuit, and a plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns along a first direction and a second direction. The sub-pixel is electrically connected with the light-emitting element through the electrical connection layer, and the portion, which is in the display region of the display substrate, of the electrical connection layer is not overlapped with the first power line in a direction perpendicular to the base substrate.