OLED Display Substrate Line Layout for RC Load Reduction
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Solution Overview
Problem
In high-resolution OLED displays, the increased pixel density and parasitic resistance-capacitance load lead to signal delay, voltage drop, and non-uniform display issues due to the arrangement of signal lines, causing color shift and display quality degradation.
Innovation Solution
The display substrate design includes a 3T1C pixel circuit with a storage capacitor, auxiliary electrode lines, and optimized signal line arrangements to reduce resistance-capacitance load, ensuring uniform power distribution and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel density is increased to achieve high-resolution display, then display resolution is improved, but parasitic resistance-capacitance load increases causing signal delay and voltage drop
Solution Approach 1:
The signal line is divided into multiple segments with intermediate connection points to other signal lines, creating a segmented transmission path that reduces the parasitic RC load on each individual segment and mitigates signal degradation
Solution Approach 2:
Multiple signal lines are merged through intermediate connection points where they intersect, allowing shared use of signal line resources and reducing the total length and parasitic load of individual signal lines while maintaining signal integrity
2Manufacturing precision
If signal lines are arranged to connect pixels in high-resolution display, then display quality is improved, but voltage drop and color shift occur due to parasitic resistance-capacitance load
Solution Approach 1:
The signal line is divided into multiple segments with intermediate connection points to other signal lines, creating a segmented transmission path that reduces the parasitic RC load on each individual segment and mitigates signal degradation
Solution Approach 2:
Intermediate connection points serve as mediators between signal lines, providing alternative signal paths that reduce the parasitic RC load on individual lines and prevent voltage drop and color shift
Data Source
AI summary
A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array in a first direction and a second direction, the first direction intersecting with the second direction. The display substrate further includes data lines extended in the first direction, and the data lines are connected in one-to-one correspondence with the sub-pixels in columns in each row of sub-pixels, so as to provide data signals respectively; the display substrate further includes auxiliary electrode lines extended in the first direction which are configured to be electrically connected with a second electrode of the light emitting element to provide a second power voltage; each of the auxiliary electrode lines is spaced from any one of the plurality of data lines by at least one column of sub-pixels.