OLED Array Substrate Shielding Layout for Stable Scan Signals
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Solution Overview
Problem
Existing OLED display technologies face challenges in optimizing the layout and electrical connections of pixel driving circuits, leading to potential interference and instability in signal transmission, which affects the performance and reliability of the display.
Innovation Solution
The array substrate incorporates a specific design with a driving circuit layer that includes pixel driving circuits, scan signal lines, and a shielding layer, where the conductive connections and scan signal lines are strategically overlapped and separated by a shielding pattern to minimize interference, and the shielding layer maintains a constant voltage, enhancing signal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan signal lines are arranged to connect to control electrodes of transistors in pixel driving circuits, then electrical connection and signal transmission are achieved, but interference and instability in signal transmission occur due to overlapping projections causing parasitic capacitance
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the scan signal lines and the conductive portions of pixel driving circuits. This shielding layer, positioned in the overlapping projection regions, acts as a mediator to block or reduce the parasitic capacitance coupling between adjacent conductive elements, thereby eliminating the harmful interference while preserving the necessary electrical connections
Solution Approach 2:
The problem of planar interference is solved by transitioning to a three-dimensional layered structure. By stacking the shielding layer at a different vertical dimension between the interfering conductive elements, the patent creates spatial separation in the thickness direction while maintaining lateral connectivity, thus reducing parasitic capacitance without affecting the electrical function
2Device complexity
If conductive portions are positioned to overlap with scan signal lines for electrical connection, then compact layout is achieved, but interference increases affecting circuit performance
Solution Approach 1:
The overlapping region between scan signal lines and conductive portions is segmented by introducing a shielding layer that divides the space into distinct zones. This segmentation allows the conductive portions to maintain their compact overlapping layout while the shielding layer creates isolated electromagnetic zones, preventing interference between adjacent signal paths
3Reliability
If shielding layer is added to reduce interference, then signal stability is improved, but device complexity increases
Solution Approach 1:
The shielding layer is designed to serve multiple functions simultaneously: it acts as an interference barrier between scan signal lines and conductive portions, provides a reference potential plane for signal stability, and can be integrated with existing pixel circuit structures. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity
Data Source
AI summary
In an array substrate, a control electrode of a driving transistor, a second electrode of a compensation transistor and a second electrode of a first reset transistor are electrically connected to a first conductive connection portion, and a first electrode of the driving transistor and a second electrode of a data writing transistor are electrically connected to a second conductive connection portion. An orthographic projection of a first conductive portion of the first conductive connection portion overlaps with an orthographic projection of a first scan signal line, and overlaps with an orthographic projection of a second scan signal line. A first shielding layer includes a first shielding pattern; in a thickness direction of the substrate, the first shielding pattern is located between the first scan signal line and the first conductive portion, and/or the first shielding pattern is located between the second scan signal line and the first conductive portion.