OLED TFT Terminal Electrode Stack to Prevent Step-Induced Shorts
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Solution Overview
Problem
Hybrid-structured organic EL display devices with polysilicon and oxide semiconductor TFTs face issues with surface step height due to overlapping wires, leading to potential short circuits between adjacent conductive layers.
Innovation Solution
The display device incorporates a specific stack of layers including polysilicon and oxide semiconductor films, with inorganic insulating films and metal films, and terminal electrodes with a layered structure of lower, middle, and upper metal layers to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If overlapping wires are formed to enhance aperture ratio, then aperture ratio is improved, but surface step height increases causing short circuits
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar wire structure to a three-dimensional stacked structure. The lower wire and upper wire are arranged in different vertical layers with insulating films between them, converting the overlapping two-dimensional arrangement into a stacked three-dimensional arrangement. This resolves the short circuit issue while maintaining the aperture ratio enhancement.
Solution Approach 2:
The patent introduces inorganic insulating films as intermediary layers between the lower wire and upper wire. These insulating films act as mediators that electrically isolate the two conductive wires while allowing them to overlap in the planar view, thus preventing short circuits while maintaining the desired aperture ratio.
2Ease of manufacture
If metal film is deposited onto stacked inorganic insulating films, then conductive layers are formed, but metal film remains at surface step height causing short circuits
Solution Approach 1:
The patent segments the metal film deposition process into multiple sequential steps. First, a lower conductive layer is formed and patterned. Then, additional metal layers are deposited and patterned to form upper conductive layers. This segmentation allows precise control over where metal exists at each stage, preventing unintended connections at surface step heights.
Solution Approach 2:
The patent performs preliminary patterning of the lower conductive layer before depositing subsequent metal layers. This preliminary action establishes the base conductive structure with proper isolation, ensuring that later metal deposits do not create short circuits. The insulating films are also formed in advance to prepare the surface for subsequent metal deposition.
Data Source
AI summary
Each of terminal electrodes including first and second terminal electrodes of a first thin-film transistor, and third and fourth terminal electrodes of a second thin-film transistor is provided with a lower metal layer, a middle metal layer, and an upper metal layer stacked sequentially. The middle metal layer has a lower electrical resistance and a lower melting point than the lower metal layer and the upper metal layer. At an end of each of the terminal electrodes, the end face of the lower metal layer and the end face of the middle metal layer are flush with each other, and the upper metal layer is provided so as to cover the end faces flush with each other.