OLED TFT Layer Structure for Lower Leakage and Simpler Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The manufacturing process of OLED display devices is complicated due to the need for separate processes for polycrystalline and oxide semiconductor patterns, leading to increased complexity and power consumption issues, particularly in devices like smart watches that display still images, where leakage current occurs.

Innovation Solution

Incorporating an insulating layer between semiconductor patterns of different types of thin-film transistors (TFTs) and positioning gate and drain electrodes on the same layer to simplify the process and improve stability, while using blocking layers to secure TFT stability and reduce screen blurring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate manufacturing processes are used for polycrystalline and oxide semiconductor patterns, then manufacturing precision can be maintained for each pattern type, but device complexity and process complexity increase significantly

Engineering Contradiction:
Improvemanufacturing precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

An insulating layer is introduced as an intermediary between the first semiconductor pattern (polycrystalline) and the second semiconductor pattern (oxide). This insulating layer acts as a protective barrier that allows different semiconductor patterns to coexist without requiring completely separate manufacturing processes, thus reducing process complexity while maintaining manufacturing precision for each pattern type.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If multiple separate processes are implemented for different semiconductor patterns, then manufacturing precision is maintained, but loss of time increases due to extended process duration

Engineering Contradiction:
Improvemanufacturing precisionVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges the manufacturing processes for different semiconductor patterns into a unified process flow. By introducing the insulating layer as a common element between polycrystalline and oxide semiconductor patterns, the patent enables simultaneous or integrated processing of different pattern types, thereby reducing the total number of separate processes and minimizing loss of time while preserving manufacturing precision.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If blocking layers are positioned at different distances below different TFTs, then screen blurring is prevented and display quality improves, but device complexity increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by positioning blocking layers at different distances below different thin-film transistors (TFTs) based on their specific functional requirements. The driving TFT, which controls the light-emitting element, has its blocking layer positioned at a first distance to optimize current control and prevent screen blurring, while other TFTs have blocking layers at a second distance. This localized differentiation improves display quality without requiring complete redesign of the entire device structure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240268162A1Light-emitting display apparatus
Publication Date: 2024.08.08 LG DISPLAY CO LTD
  • US20240268162A1 patent drawing
  • US20240268162A1 patent drawing
  • US20240268162A1 patent drawing

AI summary

The present disclosure provides a light-emitting display apparatus including a substrate including a first region and a second region, a first thin-film transistor (TFT) disposed in the first region of the substrate and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode, a second TFT disposed in the second region of the substrate and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, at least one insulating layer between the first semiconductor pattern and the second semiconductor pattern, a first blocking layer below the first semiconductor pattern, and a second blocking layer below the second semiconductor pattern.