OLED Display TFT Gate Layout With Fewer Mask Steps

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Solution Overview

Problem

The manufacturing process of OLED displays requires a large number of masks, which increases complexity and costs, and there is a need to reduce the number of masks used to simplify the process and improve efficiency.

Innovation Solution

The proposed solution involves a display device structure with a specific layer configuration that allows for the concurrent formation of certain electrodes using the same mask, reducing the number of masks needed in the manufacturing process. This includes forming the bottom gate electrode and second-first gate electrode concurrently, and the top gate electrode and second-second gate electrode concurrently, using the same mask for each pair, thereby reducing the overall thickness and complexity of the display device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional OLED manufacturing process is used, then display device functionality is achieved, but the number of masks required increases process complexity and cost

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidnumber of masks
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the formation of multiple gate electrodes (bottom gate electrode and second-first gate electrode) into a single masking step. By designing the mask pattern to simultaneously define both electrodes, the manufacturing process reduces the total number of masks required while maintaining proper electrical isolation and functional separation of the gate structures.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a multi-functional mask that serves multiple purposes: it defines the bottom gate electrode, defines the second-first gate electrode, and establishes the spatial relationship between these electrodes. This universal mask approach eliminates the need for separate masking steps for each electrode, thereby reducing process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple gate electrodes are formed separately, then precise electrical control is achieved, but the number of manufacturing steps increases

Engineering Contradiction:
Improveelectrode positioning accuracyVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges the formation of multiple gate electrodes into a single deposition and masking operation. The mask is designed with multiple patterns that simultaneously define the bottom gate electrode and the second-first gate electrode, ensuring precise relative positioning while completing both electrode formations in one step, thus improving manufacturing efficiency without sacrificing positioning accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary patterning of multiple gate electrodes simultaneously before subsequent processing steps. By establishing all gate electrode positions and shapes in advance through a single mask, the method eliminates the need for repeated alignment and positioning operations, thereby improving both precision and productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11903254B2Semiconductor device and method for fabricating the same
Publication Date: 2024.02.13 SAMSUNG DISPLAY CO LTD
  • US11903254B2 patent drawing
  • US11903254B2 patent drawing
  • US11903254B2 patent drawing

AI summary

A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer.