OLED Display TFT Stack for LTPS-Oxide Process Compatibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of low-temperature polysilicon (LTPS) and metal oxide (OXIDE) thin film transistors in display devices faces challenges due to process incompatibility, high mask plate requirements, and increased costs, which complicates the manufacturing of full-screen frame-free display products, particularly in ensuring the stability and characteristics of both transistor types.
Innovation Solution
A manufacturing method for an array substrate that forms a first thin film transistor with a polysilicon semiconductor pattern and a second thin film transistor with a metal oxide semiconductor pattern, using a method that includes forming electrode patterns and semiconductor layers in a way that minimizes process interference and ensures compatibility, such as by using shared patterning processes for forming via holes and electrodes, and optimizing the thickness of insulating layers to improve etching precision and reduce line width deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LTPS and OXIDE thin film transistors are integrated in the same display device, then the electrical characteristics and user experience are improved, but the process incompatibility and manufacturing complexity increase
Solution Approach 1:
The patent divides the transistor fabrication into separate process modules: OXIDE transistor formation (including buffer layer, semiconductor layer, gate electrode, and gate insulating layer) is completed first, followed by LTPS transistor formation. This segmentation allows each transistor type to be processed with its optimal conditions without interfering with the other, resolving the process incompatibility while maintaining both electrical characteristics.
Solution Approach 2:
The OXIDE transistor structure is formed in advance before the LTPS transistor fabrication begins. The buffer layer, semiconductor layer, gate electrode, and gate insulating layer for OXIDE transistors are prepared beforehand, allowing subsequent LTPS processing to proceed without affecting the already-formed OXIDE structure. This preliminary action eliminates process conflicts and reduces manufacturing complexity.
2Reliability
If separate processing methods are used for LTPS and OXIDE transistors, then the stability of each transistor type is ensured, but the number of mask plates and manufacturing steps increase
Solution Approach 1:
The patent merges the fabrication processes by forming both OXIDE and LTPS transistors within the same manufacturing sequence. The OXIDE transistor structure is created first, then the LTPS transistor is formed using the same equipment and process flow without requiring additional mask plates. This merging maintains transistor stability through separate processing while improving productivity by eliminating redundant steps.
Solution Approach 2:
The manufacturing process is designed to be universal, handling both OXIDE and LTPS transistor fabrication with the same equipment and process parameters. The gate insulating layer formation, etching, and electrode deposition steps serve dual purposes for both transistor types, reducing the number of specialized processes and mask plates needed while maintaining the stability of each transistor type.
3Manufacturing precision
If the gate insulating layer thickness is reduced to 1000-1500 angstroms, then the etching precision and line width control are improved, but the risk of process defects increases
Solution Approach 1:
The patent optimizes the gate insulating layer thickness to a specific range of 1000-1500 angstroms, which represents a parameter change from conventional thicker layers. This thickness optimization improves etching precision and line width control during subsequent processing steps. The parameter is carefully controlled within this range to balance manufacturing precision with process stability, preventing defects while achieving the desired precision.
Data Source
AI summary
An organic light emitting diode display device are provided. The organic light emitting diode display device includes: a substrate; a barrier layer, located on a side of the substrate; a first buffer layer, located on a side of the barrier layer; a first semiconductor layer, located on a side of the first buffer layer; a first gate insulating layer, located on a side of the first semiconductor layer; a first gate electrode, located on a side of the first gate insulating layer; a second buffer layer, located on a side of the first gate electrode; a second semiconductor layer, located on a side of the second buffer layer; a second gate insulating layer, located on a side of the second semiconductor layer; a second gate electrode, located on a side of the second gate insulating layer.