OLED Pixel Driving Timing to Reduce Slanted Line Crosstalk
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Solution Overview
Problem
OLED display devices experience slanted line crosstalk along a diagonal direction due to coupling between gate and data signals, leading to image distortion and reduced display quality.
Innovation Solution
Adjusting the timing of gate signals by implementing a timing controlling circuit that generates image data, data and gate control signals, and using data and gate driving circuits to generate and apply signals to the display panel, ensuring the rising timing of the gate1 signal occurs after the odd gate2 signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate signals are applied to control pixel lines in OLED display device, then pixel lines can be driven and displayed, but coupling between gate signals and data signals causes slanted line crosstalk and image distortion
Solution Approach 1:
The patent applies preliminary action by adjusting the timing of gate signals before they can cause harmful coupling effects. Specifically, the gate signal timing is optimized in advance to occur after the data signal has been fully applied to the pixel line, preventing the coupling distortion from occurring in the first place
Solution Approach 2:
The patent changes the timing parameter of the gate signal to resolve the crosstalk issue. By modifying when the gate signal is applied relative to the data signal, the patent eliminates the harmful coupling effect while maintaining proper pixel line control
2Reliability
If gate signal timing is adjusted to reduce crosstalk, then display quality improves, but signal synchronization complexity increases
Solution Approach 1:
The patent simplifies the timing control by making a single parameter adjustment - shifting the gate signal timing to occur after the data signal. This straightforward parameter change achieves crosstalk reduction without requiring complex multi-parameter optimization or additional control circuitry
Data Source
AI summary
A display device comprising a storage capacitor connected to a high level voltage line, a first transistor switched according to a voltage of a first capacitor electrode of the storage capacitor, a second transistor switched according to a gate2 signal and connected to a data signal and the first transistor, a third transistor switched according to a gate1 signal and connected to the storage capacitor and the first transistor, a fourth transistor switched according to the gate1 signal and connected to the storage capacitor and an initial voltage, a fifth transistor switched according to an emission signal and connected to the high level voltage and the first transistor, a sixth transistor switched according to the emission signal and connected to the first transistor, and a light emitting diode connected between the sixth transistor and a low level voltage line.