OLED Transistor Layout Crosstalk Reduction via Channel Extension
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Solution Overview
Problem
Crosstalk in OLED display panels leads to degradation in display quality, which existing technologies have not effectively addressed.
Innovation Solution
Increasing the distance between the active layer of a switching transistor connected to a data line and the active layer of an initialization transistor connected to a gate of a driving transistor, and optionally using a shielding layer to further reduce capacitance and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the distance between the active layer of the switching transistor and the active layer of the initialization transistor is increased, then crosstalk is reduced and display quality is improved, but the area occupied by the transistor layout increases
Solution Approach 1:
The patent applies dimensionality change by extending the third channel region in a direction substantially perpendicular to the first projection direction. This allows the transistors to be arranged in a three-dimensional configuration rather than purely planar, increasing the distance between active layers without proportionally increasing the footprint area on the substrate.
Solution Approach 2:
The patent implements nesting by having the third channel region extend through and beyond the boundaries of the first projection. The third active layer is positioned to overlap with regions outside the first projection, creating a nested spatial arrangement where transistor components are interlaced in the vertical dimension, effectively reducing lateral space requirements while maintaining adequate spacing for crosstalk reduction.
2Object-affected harmful factors
If a shielding layer is added between the first active layer and the third active layer, then capacitance and crosstalk are further reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The shielding layer acts as an intermediary component positioned between the first active layer and the third active layer. This intermediate structure electrically shields the third active layer from capacitive coupling with the first active layer, reducing unwanted capacitance and crosstalk. The shielding layer is connected to a reference potential to effectively terminate electromagnetic interference between the transistor layers.
3Object-affected harmful factors
If the third channel region extends beyond the first projection boundaries, then crosstalk is reduced, but the overlap region area increases
Solution Approach 1:
The patent utilizes vertical dimensionality to extend the third channel region beyond the lateral boundaries of the first projection. By arranging the third active layer to overlap with regions outside the first projection in the vertical stacking direction, the design achieves crosstalk reduction through increased spatial separation without requiring proportional increases in lateral footprint or overlap volume.
Data Source
AI summary
Provided are a display panel and a manufacturing method thereof, and a display device. At least one sub-pixel comprises a light emitting element; a first transistor comprising a first active layer comprising first and second electrode regions connected to data line and power line respectively; a capacitor; a second transistor comprising a second active layer; a third transistor comprising a third gate connected to a reset line, and a third active layer comprising a third channel region. Orthographic projections of the power line, the reset line, the third channel region and the data line are first, second, third and fourth projections respectively. The region of first, second, and third projections overlapping with each other is first region, and regions of first projection overlapping with second projection and not overlapping with third projection comprise a third region and a second region having an area not smaller than the third region.