OLED Wiring Parasitic Capacitance Reduction via Insulator
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Solution Overview
Problem
Conventional organic light-emitting display devices face challenges in reducing parasitic capacitance and signal transmission delays due to overlapping wires, which are caused by parasitic capacitance between upper and lower wires on different layers, leading to RC delays and potential electrical shorts.
Innovation Solution
The implementation of a third insulating layer with a higher dielectric constant than the second insulating layer, positioned between overlapping wires, increases the distance between wires and reduces parasitic capacitance, thereby decreasing RC delays and preventing electrical shorts. This is achieved through a specific manufacturing process involving multiple mask steps to form the necessary layers and connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wires are placed on different layers to connect TFT and capacitor, then wiring complexity is reduced and connectivity is improved, but parasitic capacitance increases due to overlapping wires
Solution Approach 1:
An insulating layer is introduced as an intermediary between the first wire (gate electrode layer) and the second wire (source/drain electrode layer) to reduce parasitic capacitance. This mediator layer physically separates the overlapping conductors while maintaining electrical insulation, thereby reducing the harmful capacitive coupling effect without compromising the wiring connectivity achieved through multi-layer configuration.
2Manufacturing precision
If photolithography process is used to form minute patterns of TFT, capacitor and wires, then manufacturing precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The gate electrode and the first wire are formed simultaneously in the same conductive layer using a single photolithography patterning step. This merging of functions reduces the total number of mask and patterning processes required, thereby decreasing manufacturing complexity and cost while maintaining the high precision pattern formation capability of photolithography for the minute patterns of TFT, capacitor, and wires.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and RC delays, improving signal transmission and reliability in organic light-emitting display devices by increasing the distance between wires and using materials with different etch rates to prevent damage during patterning.
Implementation Method 1
parasitic capacitance between upper and lower wires on different layers, leading to RC delays
Data Source
AI summary
An organic light-emitting display device includes a thin film transistor including an active layer, a gate electrode, source/drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer over the gate electrode; a pixel electrode on the first insulating layer and the second insulating layer and connected to the source or drain electrode; a first wire on the first insulating layer, of the same material as the gate electrode; a second wire on the second insulating layer to at least partially overlap the first wire and including a lower wiring layer of the same material as the pixel electrode and an upper wiring layer on the lower wiring layer, of the same material as the source/drain electrodes; and third insulating layers between the second insulating layer and the pixel electrode and between the second insulating layer and the second wire.