Omega-Gate and Tri-Gate FinFET Layout for Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in integrating short channel omega gate FinFETs and long channel FinFETs effectively, particularly in achieving optimal gate structures and undercuts within buried oxide layers to enhance device performance and reduce parasitic capacitance.
Innovation Solution
The integration of short channel omega gate FinFETs and long channel FinFETs is achieved by forming fins on a buried oxide layer, creating fin wells, and using a combination of gate dielectric and replacement gate structures, with an undercut below the short channel FinFET fin to expose its bottom surface, allowing for a unique omega-gate and tri-gate configuration respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an undercut is formed below the short channel FinFET fin to expose its bottom surface for omega-gate configuration, then gate control and device performance are improved, but manufacturing complexity increases due to additional etching and structural steps
Solution Approach 1:
The patent divides the semiconductor device into distinct short channel and long channel FinFET regions, each with tailored gate structures. The short channel FinFET receives an omega-gate configuration with undercut, while the long channel FinFET maintains a conventional planar gate, segmenting the manufacturing approach to balance performance needs with process complexity.
Solution Approach 2:
The undercut and omega-gate structure are applied locally only to the short channel FinFET region where enhanced gate control is critical for performance. The long channel FinFET retains a simpler conventional structure, applying different structural qualities to different locations based on their specific performance requirements.
2Manufacturing precision
If replacement gate structures are formed around both short and long channel fins, then threshold voltage control is improved, but manufacturing precision requirements increase due to selective gate dielectric removal
Solution Approach 1:
A sacrificial gate dielectric layer is deposited preliminary across all fin structures before patterned removal. This preliminary uniform deposition simplifies the subsequent selective removal step, as the starting point is consistent across both short and long channel devices, reducing precision requirements during the removal phase.
Solution Approach 2:
The gate dielectric layer serves as an intermediary element that is selectively removed to enable replacement gate formation. This intermediary layer facilitates the differentiation between short and long channel structures during manufacturing, allowing controlled formation of omega-gates versus conventional gates through selective etching patterns.
3Object-generated harmful factors
If fin wells are formed outside and adjoins the footprint of the fins, then parasitic capacitance is reduced, but device area increases due to additional well structures
Solution Approach 1:
Instead of extending fin wells horizontally in the plane of the fin footprint, the patent forms fin wells in the vertical dimension by etching into the buried oxide layer beneath and adjacent to the fin feet. This vertical well formation reduces lateral device area while still achieving separation to minimize parasitic capacitance effects.
Data Source
AI summary
An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.