On-Chip Processor-Accelerator Bus Bridging to Reduce Congestion
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Solution Overview
Problem
The central processing unit (CPU) based on the von Neumann architecture has low data processing efficiency for certain types of data processing, such as image data processing, due to limitations in data transmission and resource congestion on the bus.
Innovation Solution
An on-chip integrated circuit is designed with a processor circuit and an accelerator circuit, where the accelerator is connected to a second bus that bridges with the processor's first bus, allowing direct data interaction with the data storage area, and includes a dedicated data memory to reduce bus congestion and improve data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single bus is used for data transmission between processor and accelerator, then device complexity is reduced, but bus congestion increases and data processing efficiency decreases
Solution Approach 1:
The patent divides the data transmission bus into two separate buses: a first bus for processor data transmission and a second bus for accelerator data transmission. This segmentation allows independent data paths, preventing bus congestion and improving data processing efficiency while maintaining manageable complexity through modular bus design.
Solution Approach 2:
The patent introduces a bridge as an intermediary component that connects the first bus and second bus. The bridge enables controlled data interaction between the two buses, allowing the accelerator to access data storage areas independently without directly congesting the processor bus, thus resolving the contradiction between improved productivity and acceptable device complexity.
2Speed
If the accelerator shares the processor's bus, then device complexity is reduced, but data transmission speed and quality of service deteriorate
Solution Approach 1:
The patent segments the data transmission pathway by creating a dedicated second bus for the accelerator, separate from the processor's first bus. This segmentation ensures that accelerator data transmission does not share the processor bus bandwidth, maintaining high data transmission speed while introducing only minimal architectural complexity through the bridge connection.
3Productivity
If no dedicated data memory is provided for the accelerator, then device complexity is reduced, but data access capability and processing efficiency are limited
Solution Approach 1:
The patent extracts and provides a dedicated data storage area specifically for the accelerator, separating it from the processor's data storage. This extraction enables the accelerator to independently access and process data without interfering with the processor, significantly improving data processing capability while adding only minimal structural complexity through the dedicated storage region and bridge connection.
Data Source
AI summary
An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.