On-Chip Analog Block Calibration Without External Components
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Solution Overview
Problem
Conventional programmable system-on-a-chip calibration methods require external components and are inflexible, prohibiting dynamic calibration and increasing power consumption due to reliance on microcontrollers and flash memory.
Innovation Solution
A system-on-a-chip that calibrates programmable analog blocks without external components, utilizing a programmable routing fabric, non-volatile memory cells, and a microcontroller to perform dynamic iterative calibration algorithms, allowing calibration during operation and reducing power consumption by using NV latches for storing calibrated values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external calibration circuitry is used to calibrate programmable analog blocks, then calibration can be performed, but the device complexity increases and power consumption increases
Solution Approach 1:
The patent merges the calibration functionality into the existing programmable logic array and routing fabric of the system-on-a-chip. The calibration logic is implemented using the same programmable resources that perform logical functions, eliminating the need for separate external calibration circuitry. This integration maintains calibration capability while reducing device complexity and power consumption.
Solution Approach 2:
The programmable logic array and routing fabric are designed to serve multiple functions: they perform both logical operations during normal system operation and calibration operations when needed. This multi-functionality allows the same hardware resources to be used for both computation and calibration, eliminating dedicated calibration circuitry.
2Reliability
If flash memory is used to store calibration values, then calibration data can be stored, but power consumption increases
Solution Approach 1:
The patent uses different storage mechanisms with different power characteristics for different calibration scenarios. NV latches provide non-volatile storage with low power consumption for retaining calibration values, while RAM provides volatile but faster access storage when power is available. This localized optimization of storage technology reduces overall power consumption compared to using flash memory for all calibration data storage.
3Reliability
If microcontroller is used to perform calibration, then calibration algorithms can be executed, but dynamic calibration during operation is prohibited
Solution Approach 1:
The patent implements dynamic calibration capability by integrating calibration logic directly into the programmable logic array, which can be reconfigured and executed at any time during system operation. This allows calibration to be performed dynamically without waiting for microcontroller boot-up or intervention, enabling real-time adaptation to changing operating conditions.
Solution Approach 2:
The system performs calibration autonomously using its own programmable logic resources without requiring external control or microcontroller intervention. The calibration logic is self-contained within the programmable logic array and can execute calibration algorithms independently, enabling the system to self-calibrate during operation.
4Reliability
If conventional calibration methods are used, then calibration can be performed, but additional peripheral circuitry is required which consumes power and increases space
Solution Approach 1:
The patent combines calibration functionality with the existing programmable logic array and routing fabric, eliminating the need for separate peripheral calibration circuitry. The same hardware resources that perform logical functions are used to perform calibration, reducing the total quantity of circuitry required on the chip.
Solution Approach 2:
The programmable logic array and routing fabric are designed to be universal resources that can perform both logical operations and calibration operations. This multi-functionality eliminates the need for dedicated calibration peripheral circuitry, reducing space and power consumption while maintaining full calibration capability.
Data Source
AI summary
A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.