On-Chip Antenna Structures for High-Frequency Chip Communication
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Solution Overview
Problem
As semiconductor chips miniaturize and packaging density increases, conventional wiring techniques face limitations due to inductive, resistive, and capacitive delays, impairing circuit performance, especially at high clock frequencies, and require more efficient communication methods between closely spaced chips.
Innovation Solution
The use of microbumps, redistribution layers (RDLs), and structures like TSVs, copper pillars, and inter-metal layers to form various types of antennas such as patch, dipole, spiral, and slot antennas on-chip, reducing inductive, resistive, and capacitive delays and enhancing RF signal communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wiring techniques are used for communication between chips, then circuit performance is maintained at lower frequencies, but inductive, resistive and capacitive delays significantly impair performance at high clock frequencies in the GHz range
Solution Approach 1:
The patent replaces conventional mechanical/electrical wiring techniques with electromagnetic radiation-based communication. Antennas are integrated directly onto the semiconductor chip to transmit and receive RF signals, substituting the physical conductor-based signal transmission with wireless electromagnetic communication, thereby eliminating inductive, resistive and capacitive delays associated with conventional wiring at high frequencies
Solution Approach 2:
The patent transitions from planar two-dimensional wiring layouts to three-dimensional antenna structures. By incorporating vertical elements such as patch antennas with ground planes and elevated conductive structures, the design utilizes the third dimension (height above the chip surface) to create effective radiating elements that overcome the limitations of flat, two-dimensional circuit traces
2Productivity
If semiconductor chips are miniaturized to increase device speed and circuit density, then device speed and circuit density increase, but the area available for communications conductors becomes increasingly limited
Solution Approach 1:
The patent utilizes three-dimensional antenna structures that extend vertically from the chip surface, employing patch antennas with ground planes separated by dielectric layers. This vertical dimension allows effective antenna operation with minimal planar footprint, enabling RF communication functionality without consuming excessive lateral space on miniaturized chips
Solution Approach 2:
The patent integrates antenna structures directly with the semiconductor chip fabrication process, combining RF communication functionality with the existing chip architecture. Conductive layers used for chip interconnection are simultaneously configured to form antenna elements, merging communication functions with the chip's existing structural components
3Ease of operation
If conventional bond-wires and microbumps are used for connections, then chip-to-chip communication is enabled, but inductive, resistive and capacitive delays significantly impair circuit performance at high frequencies
Solution Approach 1:
The patent replaces mechanical connection methods (bond-wires and microbumps) with integrated on-chip antenna structures. Instead of relying on physical connectors that introduce parasitic inductance, resistance and capacitance, the design uses electromagnetic radiation from compact antenna elements to transmit signals, eliminating the need for extended conductive paths and their associated losses at high frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective communication between semiconductor chips by reducing delays and increasing communication efficiency, supporting higher frequencies and complex operations within advanced electronic devices.
Implementation Method 1
one or more metallic structures formed by through-silicon vias (TSVs), microbumps, copper pillars, or redistribution layers with or without inter-metal layers in the upper or lower chips can form various types of antennas such as patch, dipole, spiral, slot, and the like on-chip
Data Source
AI summary
An antenna formed on a semiconductor structure having a substrate with electrical circuits thereon operationally related to the functionality of an antenna and one or more metallic structures formed by a through silicon via, microbump, copper pillar, or redistribution layer proximate to the substrate. The one or more metallic structures form a radiating element of the antenna. Exemplary antennas thus formed can include a slot antenna, a WLAN slot antenna, a planar invented F antenna (PIFA), a spiral antenna, a dipole antenna, a Yagi antenna, a planar dipole antenna, a vertical dipole antenna, a patch antenna, a helical antenna, a loop patch antenna, and combinations thereof.