On-Chip Backup Pages for Shared Virtual Memory Consistency
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Solution Overview
Problem
In multi-core processors, cache coherence issues lead to increased communication costs and design complexity as the number of cores grows, with existing software cache coherence mechanisms like Twin/Diff causing high off-chip access latency and reduced execution efficiency due to cache replacement algorithms.
Innovation Solution
A method where data content in a shared virtual memory page is copied into off-chip memory, with a backup page stored in on-chip memory before write operations, ensuring data consistency and reducing cache contention, allowing faster access speeds and improved program execution by maintaining the working page in the cache during updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware cache coherence protocol is used, then cache consistency is maintained, but communication costs and design complexity increase linearly with core quantity
Solution Approach 1:
The patent segments the cache coherence problem by introducing scope-based partitioning, where shared variables are divided into different scopes (global, local, private) with different coherence requirements. This allows selective application of coherence protocols only where needed, reducing overall communication overhead while maintaining consistency for shared variables.
Solution Approach 2:
The patent applies local quality by implementing differential coherence policies for different memory scopes. Global shared variables maintain full coherence through hardware protocols, while local and private variables use relaxed coherence models, allowing each region to have optimized coherence characteristics suited to its access patterns.
2Reliability
If Twin/Diff mechanism is used for software cache coherence, then data consistency is ensured, but off-chip access latency increases and execution efficiency decreases
Solution Approach 1:
The patent applies preliminary action by pre-loading backup pages into on-chip memory before they are needed for diff operations. This advance preparation ensures that when coherence checks are needed, the comparison data is already available in fast on-chip memory, eliminating latency-causing off-chip accesses.
Solution Approach 2:
The patent introduces on-chip memory as an intermediary layer between off-chip memory and cache. This intermediary stores backup pages locally, providing fast access for diff operations without requiring direct off-chip memory access, thus reducing latency while maintaining data consistency verification.
3Reliability
If backup pages are stored in off-chip memory, then data consistency can be verified, but access speed decreases due to off-chip memory limitations
Solution Approach 1:
The patent changes the dimensional aspect of storage by moving backup pages from off-chip memory (external dimension) to on-chip memory (internal dimension). This spatial repositioning brings the verification data closer to the processing units, dramatically increasing access speed while maintaining the data consistency verification capability.
Data Source
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AI summary
Embodiments of the present invention provide a method and an apparatus for sharing data on a computing node, including: copying a shared virtual memory page to which a first process requests access into off-chip memory of a computing node, and using the shared virtual memory page copied into the off-chip memory as a working page of the first process; and before the first process performs a write operation on the working page, creating, in on-chip memory of the computing node, a backup page of the working page, so as to back up original data of the working page. In the embodiments of the present invention, by using programmable on-chip memory of a computing node, before a write operation is performed on a working page, page data is backed up in the on-chip memory, so as to ensure data consistency when multiple processes perform an operation on a shared virtual memory page while accessing off-chip memory as less as possible and improving a speed of a program.