On-Chip Buffer Memory Hierarchy for Video Processor Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high bandwidth memory systems for real-time video encoding, such as those using external DRAM chips, result in excessive power consumption due to high worst-case bandwidth and latency requirements, which are not adequately met by on-chip caches, especially in portable applications.
Innovation Solution
A memory hierarchy comprising an internal memory with a buffer for storing reference frames and an external transfer circuit on a chip, which minimizes external memory bandwidth usage, hides latency, and optimizes long burst exchanges to reduce power consumption and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external DRAM chips are used to provide full worst case bandwidth for real time video encoding, then bandwidth requirement is met, but power consumption becomes excessive
Solution Approach 1:
The patent segments the memory system into multiple levels: on-chip buffers for frequently accessed reference frame data and external DRAM for full frame storage. This segmentation allows the system to serve bandwidth-critical operations from low-power on-chip memory while using external memory only when necessary, thereby reducing overall power consumption while maintaining required bandwidth for real-time video encoding.
Solution Approach 2:
The patent implements local quality by providing high-speed on-chip buffering specifically for reference frame data that requires frequent access during motion compensation, while the less frequently accessed full frame data resides in external DRAM. This localized high-performance memory allocation optimizes power efficiency by keeping only the most critical data paths using the power-intensive on-chip resources.
2Use of energy by moving object
If on-chip caches are used to reduce power consumption, then power efficiency improves, but worst case performance and bandwidth requirements are not met
Solution Approach 1:
The patent applies preliminary action by pre-loading reference frame data into on-chip buffers before it is needed for motion compensation operations. This advance preparation ensures that when bandwidth-critical operations occur, the data is already available in high-speed on-chip memory, preventing performance degradation while maintaining power efficiency during the actual processing operations.
Solution Approach 2:
The on-chip buffer acts as an intermediary between the external DRAM and the video encoding processor. It mediates bandwidth requirements by absorbing peak demand during motion compensation operations, translating intermittent high-bandwidth needs into sustained lower-bandwidth external memory access, thereby protecting the system from power consumption spikes while meeting performance requirements.
3Productivity
If external memory is accessed frequently to meet bandwidth specifications, then bandwidth requirement is satisfied, but latency increases and power consumption rises
Solution Approach 1:
The patent segments memory access patterns by directing reference frame data accesses to on-chip buffers while full frame data accesses go to external DRAM. This segmentation eliminates latency for the time-critical reference frame operations by keeping that data locally available, while external memory access occurs only for non-time-critical full frame operations.
Solution Approach 2:
The on-chip buffer serves as an intermediary that absorbs external memory latency by maintaining local copies of reference frame data. When the processor needs data during motion compensation, it accesses the low-latency on-chip buffer instead of the high-latency external DRAM, effectively hiding external memory latency from the critical processing path.
Data Source
AI summary
An apparatus generally having an internal memory and an external transfer circuit is disclosed. The internal memory may be disposed on a chip and may contain at least one first buffer for storing a subset of at least one reference frame (i) suitable for motion compensation and (ii) stored in an external memory off the chip. A size of the at least one first buffer generally exceeds one row of blocks in the reference frame. The external transfer circuit may be disposed on the chip and configured to transfer the subset from the external memory to the internal memory.