On-Chip Bus Packet Router for Multi-SoC Communication
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Solution Overview
Problem
Current on-chip bus architectures in FPGA and SoC devices are limited in supporting multiple FPGAs on a chip or across multiple chips, lacking burst support, bidirectionality, and full duplex communications, and require software modifications for data routing between devices.
Innovation Solution
A system employing packet routers with a router bridge and arbiter to route data communications between SoC devices, enabling full-duplex communications, burst support, and flow-control signaling, while maintaining On-Chip Bus protocols by translating address and data lines into data packets and using arbitration schemes for message forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an address-based on-chip bus architecture is used, then simple read/write operations are enabled, but the system cannot support multiple FPGAs on a chip or across multiple chips
Solution Approach 1:
The system segments the on-chip bus functionality by introducing individual control buses for each FPGA device. Each FPGA receives control signals through its dedicated control bus, allowing independent addressing and control. This segmentation enables multiple FPGAs to coexist on the chip with distinct address spaces, resolving the limitation of single-device address-based architecture.
Solution Approach 2:
The patent introduces control buses as intermediary channels between the master device and multiple FPGA slaves. These control buses act as mediators that carry control signals, address information, and handshaking protocols to the appropriate FPGA devices, enabling complex multi-device communication while maintaining a unified system architecture.
2Adaptability or versatility
If a chip-to-chip architecture with individual control buses is used, then multiple FPGA support is enabled, but software must be changed with each modification to ensure data reaches the intended physical device
Solution Approach 1:
The control bus architecture implements universal control signals that can address and control any FPGA device in the system through a standardized protocol. The control buses carry generic control commands, address fields, and data that can be routed to any target device, eliminating the need for device-specific software modifications. The system provides a unified interface that works across different FPGA instances and chip configurations.
3Productivity
If traditional on-chip bus architecture is used, then basic data transfer is enabled, but burst support, bidirectionality, and full duplex communications are not provided
Solution Approach 1:
The control bus architecture implements dynamic communication capabilities including bidirectional data flow and full-duplex operation. The control signals enable flexible direction control, allowing data to flow in either direction on the same physical bus. Burst support is achieved through dynamic control signal sequences that can initiate and manage continuous data transfers, adapting the communication mode based on system requirements.
Solution Approach 2:
The control bus system enables continuous data transfer through burst mode operation, where multiple data words can be transferred in a single continuous transaction without requiring repeated address setup. The handshaking protocols and control signals maintain continuous useful action by managing data flow, acknowledgments, and flow control, maximizing bus utilization and communication efficiency.
Data Source
AI summary
A system and related method for routing Modem Hardware Abstraction Layer (MHAL) On-Chip Bus (MOCB) protocol data communications between a first system on a chip (SoC) device and at least one second SoC device abstracts the physical layer across one or more physical devices via one or more packet routers, the packet routers capable of receiving MOCB commands and responses and generating data packets based on the commands and responses, the data packets having a first word indicating the destination device. Other packet routers determine the destination of inbound data packets, and whether to bypass or receive the data packets, based on the first word (without having to fully decode the data packets) and deserialize received packets into MOCB commands and responses, forwarding the commands or responses to the intended destination SoC device.