On-Chip Bus Switch Points for SOC Power and Delay Reduction

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Solution Overview

Problem

Conventional on-chip bus architectures in highly integrated System-on-Chip (SOC) systems face challenges in achieving desired performance due to increased inductance, resistance, and capacitance of bus wires, leading to higher power consumption and communication delays, especially when functional block cores with high data traffic are connected using conventional bus architectures.

Innovation Solution

The proposed on-chip bus architecture reduces inter-switch link usage by allowing functional block cores with high data traffic to share a common switch point, directly connecting switch points to multiple functional block cores, and arranging inter-switch links in a mesh pattern to minimize the need for intermediate links, thereby reducing power consumption and communication delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bus architecture is used in highly integrated SOC system, then system compatibility is maintained, but inductance, resistance and capacitance of bus wires increase leading to performance degradation

Engineering Contradiction:

Improvesystem performanceVSAvoidbus wire characteristics

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The conventional bus architecture is segmented into switch points and inter-switch links arranged in a mesh pattern. This segmentation allows data to be transmitted through multiple shorter paths rather than long direct bus wires, reducing the effective wire length and associated inductance, resistance, and capacitance while maintaining system functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a traditional one-dimensional linear bus architecture to a two-dimensional mesh architecture. By arranging switch points and inter-switch links in a mesh pattern, data can traverse multiple dimensions and paths, effectively reducing the impact of wire length and electrical characteristics on signal transmission.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If functional block cores with high data traffic are connected using conventional bus architecture, then connectivity is achieved, but power consumption and communication delays increase

Engineering Contradiction:

Improvedata communication capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

Multiple functional block cores with high data traffic are merged and connected to a common switch point. This consolidation allows these cores to share the same communication infrastructure, reducing the total number of active inter-switch links and thereby decreasing overall power consumption while maintaining high data communication capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Switch points serve as intermediary nodes that mediate data communication between functional block cores. By using switch points as intermediaries, data can be routed more efficiently through the mesh architecture, reducing communication delays and the energy required for signal transmission compared to direct conventional bus connections.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If functional block cores with high data traffic are connected using conventional bus architecture, then connectivity is achieved, but communication delays increase

Engineering Contradiction:

Improvedata communication capabilityVSAvoidcommunication delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The communication path is segmented into multiple shorter segments through switch points and inter-switch links arranged in a mesh. This segmentation enables data to traverse shorter distances and reduces the number of hops required, thereby decreasing communication delays while maintaining high data communication capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The mesh architecture provides dynamic routing capabilities where data can be directed through different paths based on real-time conditions. This dynamic nature allows the system to optimize communication routes and minimize delays by selecting the most efficient paths for data transmission.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8051238B2On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture

Publication Date: 2011.11.01 SAMSUNG ELECTRONICS CO LTD

AI summary

An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.