On-Chip Cache for Nonvolatile Memory Program Failure Recovery
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Solution Overview
Problem
Nonvolatile memory systems, particularly Multi-Level Cell (MLC) memory systems, face challenges in handling program failures due to increased precision requirements and potential data corruption, leading to slower programming speeds and resource-intensive error handling.
Innovation Solution
Implementing an on-chip cache that maintains a safe copy of data before writing it to the nonvolatile memory array, allowing for data recovery in case of write failures without the need for additional controller resources, enabling parallel data transfer and efficient management of data storage across multiple memory states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a safe copy of data is maintained in controller RAM to handle program failures, then data reliability is improved, but controller resource consumption increases and programming speed decreases
Solution Approach 1:
The patent introduces an on-chip cache as an intermediary component between the controller and nonvolatile memory array. The cache maintains safe copies of data locally on the memory chip, serving as a mediator that provides data recovery capability without burdening the controller's RAM resources. This allows the controller to operate more efficiently while the cache handles the safety backup function.
Solution Approach 2:
The patent moves the safe copy storage from the controller's RAM (one dimension) to an on-chip cache located on the memory chip itself (another dimension). This spatial redistribution of storage resources allows the controller to release RAM memory while the cache on the chip continues to maintain data safety, effectively resolving the resource conflict.
2Reliability
If controller RAM is used to maintain safe copies of data, then data recovery capability is improved, but the amount of available controller RAM for other operations decreases
Solution Approach 1:
The patent extracts the safe copy storage function from the controller's RAM and relocates it to an on-chip cache. This separation allows the controller's RAM to be fully available for other operations while the cache independently maintains data safety copies, effectively taking out the burden from the controller's memory resources.
3Productivity
If data is written directly to nonvolatile memory array without intermediate caching, then programming speed is improved, but data integrity during write operations is compromised
Solution Approach 1:
The patent implements preliminary action by maintaining safe copies of data in the on-chip cache before writing to the nonvolatile memory array. This advance preparation ensures that if a write failure occurs, the data can be recovered from the cache without requiring re-programming, thus protecting data integrity while allowing fast direct writing.
Data Source
AI summary
In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array.