On-Chip Cache Row-Column Addressing for Small-Packet Storage
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Solution Overview
Problem
Existing chip designs face inefficiencies in storage space utilization and excessive power consumption due to the inability to effectively handle packets with small packet lengths, leading to wasted memory space and increased area requirements.
Innovation Solution
An on-chip cache apparatus utilizing a cache module and memory module to store packets using row and column addresses, allowing multiple packets to be cached and stored simultaneously, with conflict handling mechanisms to optimize space utilization and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the chip increases dominant frequency and stacking resources to improve performance, then performance indicators improve, but chip area consumption increases excessively
Solution Approach 1:
The patent implements dynamic resource allocation through a state machine that monitors packet arrival patterns and dynamically switches between different cache modes (single-packet mode, multi-packet mode, and bypass mode). This allows the system to adapt to varying traffic conditions and optimize the balance between performance and area usage, rather than using a fixed high-performance design that consumes excessive area.
Solution Approach 2:
The system changes operational parameters based on packet characteristics. When small packets are detected, the cache depth and allocation strategy are adjusted to accommodate multiple packets per row. The state machine transitions between different operational states (STATE_0, STATE_1, STATE_2) that modify cache behavior, enabling the same hardware to efficiently handle different packet sizes and patterns without requiring excessive resources.
2Adaptability or versatility
If the chip design allocates large storage space to handle small packets, then small packet processing capability improves, but power consumption increases excessively
Solution Approach 1:
The patent employs a state machine that dynamically adjusts cache behavior based on packet arrival patterns. When small packets are detected, the system transitions to multi-packet cache mode which efficiently utilizes storage space. When traffic patterns change, the state machine can switch to bypass mode or single-packet mode, reducing power consumption by deactivating or minimizing cache operations. This dynamic adaptation eliminates the need for continuously operating large cache structures.
Solution Approach 2:
The patent extracts and handles small packets differently from regular packets by implementing a specialized multi-packet mode. Instead of using the same cache structure for all packets, the system identifies small packets and routes them through a optimized path that consolidates multiple packets into fewer cache rows. This extraction of the small packet handling function reduces the overall cache size needed and lowers power consumption.
3Device complexity
If each row stores only one packet according to row address, then address management simplifies, but storage space utilization deteriorates
Solution Approach 1:
The patent segments the cache addressing into two levels: row address for selecting cache lines and column address for selecting specific packets within those lines. This segmentation allows multiple packets to be stored in a single row by using different column addresses. The state machine manages the complexity by automatically handling column address assignment when in multi-packet mode, maintaining relatively simple address management while dramatically improving storage utilization.
Solution Approach 2:
The patent adds a column address dimension to the traditional row-address-only cache structure. By introducing column addresses, the system can store multiple packets within a single row, effectively transforming from a one-dimensional (row-only) addressing scheme to a two-dimensional (row-column) scheme. This dimensional change enables efficient packing of small packets without significantly complicating the address management logic, as the state machine handles the coordination.
Data Source
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AI summary
The present application provides an on-chip cache apparatus, an on-chip cache on-chip cache read-write method and a computer-readable medium, the on-chip cache apparatus includes: a read-write processing module, a cache module and a memory module; the read-write processing module is connected with the cache module and the memory module respectively, and is configured to store packets into the cache module and the memory module, read packets stored in the cache module and the memory module, and transfer packets cached in the cache module to the memory module for storing; the cache module is connected with the memory module through the read-write processing module, and includes at least one cache register configured to temporarily cache packets; and the memory module is connected with the read-write processing module, and is configured to store the packets cached in the cache module.