On-Chip Capacitor Calibration via Variable MOS Integration
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Solution Overview
Problem
Existing on-chip capacitors in silicon semiconductor chips face significant challenges in accurately predicting capacitance values, often resulting in variations of 10% or more due to manufacturing and temperature factors, leading to high rejection rates and decreased yields, particularly in RF and analog circuits.
Innovation Solution
Incorporating a pair of variable MOS capacitors in parallel with fixed value MIMCAP and VNCAP capacitors, and using a back-to-back connection of these MOS capacitors to adjust and optimize capacitance values, allowing for precise calibration within 1% to 5% of the target value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional fixed-value MIMCAP or VNCAP capacitors are used, then the manufacturing process is simple, but the capacitance value varies by 10% or more due to manufacturing and temperature variations
Solution Approach 1:
The patent combines a fixed-value capacitor (MIMCAP or VNCAP) with a variable MOS capacitor into a single integrated capacitor structure. The fixed-value capacitor provides the base capacitance, while the variable MOS capacitor allows for adjustment of the total capacitance value, thereby achieving precise capacitance control within 1% to 5% of the target value.
Solution Approach 2:
The patent introduces a variable MOS capacitor that can dynamically adjust its capacitance value through voltage control. This dynamic element allows the total capacitance to be tuned after manufacturing, compensating for variations caused by manufacturing processes and temperature changes.
2Reliability
If no adjustment mechanism is provided, then the device complexity is low, but the rejection rate is high due to capacitance variations exceeding acceptable tolerances
Solution Approach 1:
The patent incorporates the variable MOS capacitor and adjustment mechanism during the initial manufacturing process, allowing capacitance calibration to be performed before the chip is shipped. This preliminary adjustment ensures that each capacitor is calibrated to its target value, reducing rejection rates and improving chip yield.
Solution Approach 2:
The patent changes the capacitance parameter of the MOS capacitor through voltage control to compensate for manufacturing variations. By adjusting the voltage applied to the MOS capacitor, the total capacitance can be fine-tuned to achieve the desired precision within 1% to 5% of the target value.
3Manufacturing precision
If a variable MOS capacitor is added in parallel with the fixed-value capacitor, then the capacitance precision is improved to within 1% to 5%, but the device complexity increases
Solution Approach 1:
The patent merges the fixed-value capacitor and variable MOS capacitor into a single integrated structure, sharing common electrodes and insulation layers. This merging approach reduces the overall device complexity compared to using separate capacitors, while still achieving the precision benefit of combining both capacitor types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of precision on-chip capacitors, improving RF matching circuits and analog circuits by allowing precise capacitance adjustments, reducing production errors, and enhancing overall chip accuracy.
Implementation Method 1
a pair of variable MOS capacitors coupled in parallel with each of the fixed value capacitors to adjust the total output value of each capacitor in the group
Data Source
AI summary
One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.