On-Chip Capacitor Layout for Low-Inductance Power Stabilization

Solution Overview

Problem

Conventional semiconductor devices face challenges in stabilizing power supply and reducing inductance components, particularly during high-speed operations, due to the length and configuration of wiring for capacitors mounted on wiring substrates.

Innovation Solution

A semiconductor device configuration that includes a capacitor with a parallel flat-plate structure, where the capacitor's electrodes are connected to supply terminals via shorter bonding wires, and the capacitor is integrated directly onto semiconductor memory chips, reducing the overall thickness and inductance, and utilizing a re-distribution layer for further connectivity optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a capacitor is mounted on a wiring substrate, then power supply stabilization is achieved, but wiring length increases and inductance components increase

Engineering Contradiction:

Improvepower supply stabilizationVSAvoidwiring length

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The capacitor is integrated directly onto the semiconductor chip, merging the capacitor component with the chip structure. This eliminates the need for separate wiring substrate mounting and long bonding wires, thereby reducing wiring length and inductance while maintaining power supply stabilization functionality

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The capacitor is positioned in the thickness direction (Z-direction) of the semiconductor chip, utilizing the vertical dimension rather than horizontal plane mounting. This allows the capacitor electrodes to be connected to supply terminals through short bonding wires extending in the thickness direction, reducing the overall wiring length and inductance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If a capacitor is mounted on a wiring substrate, then power supply stabilization is achieved, but inductance components increase

Engineering Contradiction:

Improvepower supply stabilizationVSAvoidinductance components

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The capacitor is integrated directly onto the semiconductor chip, merging the capacitor component with the chip structure. This eliminates the need for separate wiring substrate mounting and long bonding wires, thereby reducing wiring length and inductance while maintaining power supply stabilization functionality

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The capacitor is designed with a parallel flat-plate structure where the electrode area in the plane direction is larger than the electrode area in the thickness direction. This geometric parameter optimization reduces the inductance of the capacitor structure itself, complementing the reduction achieved by shortening the bonding wire length

Inventive Principle:

Principle #35Parameter changes

3Ease of operation

If capacitor electrodes are connected to supply terminals with long wiring, then connectivity is achieved, but inductance components increase and high-speed operation is hindered

Engineering Contradiction:

ImproveconnectivityVSAvoidhigh-speed operation capability

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The capacitor is positioned in the thickness direction (Z-direction) of the semiconductor chip, utilizing the vertical dimension rather than horizontal plane mounting. This allows the capacitor electrodes to be connected to supply terminals through short bonding wires extending in the thickness direction, reducing the overall wiring length and inductance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor is designed with a parallel flat-plate structure where the electrode area in the plane direction is larger than the electrode area in the thickness direction. This geometric parameter optimization reduces the inductance of the capacitor structure itself, complementing the reduction achieved by shortening the bonding wire length

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20230411366A1Semiconductor device

Publication Date: 2023.12.21 KIOXIA CORP

AI summary

A semiconductor device according to the present disclosure includes: a semiconductor chip including a first supply terminal and a second supply terminal; a passive element provided on the semiconductor chip, the passive element including a first electrode, a dielectric provided on the first electrode, and a second electrode provided on the dielectric; a first wiring which electrically connects the first supply terminal and the first electrode to each other; and a second wiring which electrically connects the second supply terminal and the second electrode to each other.