On-Chip Capacitor Interstitial Projections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current MIM capacitors face challenges in achieving higher capacitance within the same or smaller component sizes, as their multi-layer structure limits further enhancement of layer-to-layer capacitance.
Innovation Solution
The design introduces a multi-layer on-chip capacitor with intermeshing tines that project between layers, creating an interstitial capacitance in addition to layer capacitance, allowing for increased capacitance without the need for additional layer-to-layer connections, and varying production methods such as local interconnect or trench dual damascene etching can be used depending on technology size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional MIM capacitor multi-layer structure is used, then layer-to-layer capacitance is provided, but total capacitance density is limited
Solution Approach 1:
The patent extends the capacitance-generating structure from the planar layer dimension into the vertical interstitial dimension by adding projections that extend between adjacent layers. This dimensional transition allows capacitance to be generated in the previously underutilized interstitial space, effectively adding another dimension for capacitance accumulation without increasing layer count or planar area.
Solution Approach 2:
The projections are nested within the interstitial spaces between adjacent capacitor layers, utilizing the existing multi-layer structure's voids. This nesting approach allows the capacitance-generating projections to be embedded within the established layer framework, maximizing space utilization without adding external structural complexity.
2Quantity of substance
If projections are added to create interstitial capacitance, then total capacitance increases by 70-120%, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the projection formation step with existing capacitor manufacturing processes. The projections are formed as part of the standard interconnect or via formation steps using local interconnect or trench dual damascene etching, consolidating multiple functions into unified process steps rather than adding separate manufacturing operations.
Solution Approach 2:
The patent adjusts manufacturing parameters such as etching depth, projection height, and material deposition thickness to optimize capacitance while maintaining compatibility with standard fabrication processes. By controlling these parameters within existing process windows, the design achieves enhanced capacitance without requiring fundamentally new manufacturing capabilities.
3Quantity of substance
If component size is reduced to increase capacitance density, then capacitance per area increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the capacitance-generating structure into multiple discrete projections distributed throughout the interstitial spaces. This segmentation distributes the total capacitance across many smaller elements, reducing the precision requirements for each individual projection while maintaining high overall capacitance density through cumulative effect.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the projections in high-density areas have optimized dimensions and spacing tailored to local space constraints, while maintaining overall design consistency. This local optimization allows high capacitance density in compact regions without uniformly increasing precision requirements across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 70-120% increase in total capacitance compared to traditional MIM capacitors, with no increase in processing steps or overall dimensions, effectively enhancing capacitance density.
Implementation Method 1
the multi-layer capacitor further includes a plurality of projections from said tines, said projections extending between frames of adjacent layers so as to provide an interstitial capacitance between the layers
Implementation Method 2
MIM (Metal: Insulator: Metal) capacitors are known for their use in RF devices due to their high capacitance and low resistance
Data Source
AI summary
An on-chip capacitor having a plurality of capacitor layers. Each capacitor layer includes a pair of frames. A first frame of the pair is electrically connected to first frames on each other capacitor layer and a second frame of the pair is electrically connected to second frames on each other capacitor layer. A plurality of tines project from each frame within the respective capacitor layer. The tines from each frame mesh so as to form an array of sequentially alternating tines from each frame to provide a layer capacitance within the capacitor layer. The multi-layer capacitor further includes a plurality of projections from the tines. The projections extend between frames of adjacent capacitor layers so as to provide an interstitial capacitance between the capacitor layers. The total capacitance of the on-chip capacitor is the sum of each layer capacitance and each interstitial capacitance.