On-Chip Clock Controller for Power-Stable At-Speed Testing
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Solution Overview
Problem
In testing large-scale semiconductor devices, the demand for current at higher clock speeds can cause power droop, leading to failed at-speed tests or reduced performance during testing.
Innovation Solution
A semiconductor device with an on-chip clock controller (OCC) that provides shift pulses and capture pulses to control clock speeds, allowing for an increased number of fast/slow clock pulses without increasing the number of shift registers, and enabling different sequences of shift and capture phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock speed is increased for at-speed testing, then testing speed and device exercise capability are improved, but current demand increases causing power droop and test failures
Solution Approach 1:
The patent implements periodic action by alternating between slow clock phases and fast clock phases in a cyclic manner. The slow phases allow power stabilization and reduce cumulative power droop, while fast phases perform the actual at-speed testing. This periodic modulation of clock speed resolves the contradiction by enabling high-speed testing without continuous power overload.
Solution Approach 2:
The patent applies preliminary action by performing slow clock phases before fast clock phases to pre-charge power networks and stabilize voltage levels. This preparatory slow phase ensures that when fast clock phases begin, the power infrastructure is ready to handle the increased current demand, preventing power droop-induced test failures.
2Quantity of substance
If multiple shift registers are added to increase clock pulse capacity, then the number of available clock pulses is improved, but device complexity and area increase
Solution Approach 1:
The patent applies universality by making existing shift registers perform multiple functions: they generate both slow clock pulses and fast clock pulses depending on the operational phase. The same hardware infrastructure is reused across different clock speed regimes, eliminating the need for additional shift registers while maintaining increased pulse capacity through temporal multiplexing.
Solution Approach 2:
The patent implements dynamics by making the clock generation system adaptive and reconfigurable. The shift registers dynamically switch between generating slow clocks and fast clocks based on test requirements. This dynamic behavior allows the system to provide variable clock pulse quantities without adding fixed hardware, resolving the contradiction between pulse capacity and complexity.
3Ease of operation
If a single clock speed is used throughout testing, then device operation is simplified, but power management capability and test flexibility are reduced
Solution Approach 1:
The patent applies dynamics by implementing a dynamic clock speed selection mechanism that automatically transitions between slow and fast clock phases based on test stage and power conditions. This dynamic operation maintains ease of use through automated control while achieving adaptability in power management, allowing the system to optimize performance and power consumption without manual intervention.
Solution Approach 2:
The patent implements parameter changes by varying the clock speed parameter throughout the test cycle. The system changes from slow clock parameters during initialization and power-stable phases to fast clock parameters during at-speed testing phases. This parameter modulation enables flexible power profile management while maintaining operational simplicity through automated parameter switching.
Data Source
AI summary
A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.