On-Chip Clock Jitter Measurement via Synchronous Data Path
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Solution Overview
Problem
Accurately quantifying clock jitter in high-frequency integrated circuit chips is challenging due to the difficulty in modeling mixed-signal and distributed sources of jitter, leading to inaccurate off-chip measurements that can result in unnecessary performance limitations or timing errors.
Innovation Solution
An on-chip method using a synchronous data path with a launch element and a capture element, coupled with a programmable delay and controller, to measure clock jitter by comparing data sent and received, adjusting timing settings, and determining timing violations, thereby reducing measurement error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If off-chip measurement techniques are used to measure clock jitter, then the measurement can be performed with standard equipment, but the measurement accuracy deteriorates due to additional timing uncertainty introduced by output drivers, PCB traces, and frequency division
Solution Approach 1:
The invention extracts the measurement function from the external test environment and integrates it directly into the chip. Launch and capture elements are embedded on-chip to perform jitter measurement internally, eliminating the need to send signals through output drivers and PCB traces that introduce timing uncertainty. This extraction of the measurement function to the chip interior resolves the contradiction by maintaining measurement accessibility while dramatically improving accuracy.
Solution Approach 2:
The invention introduces on-chip launch and capture elements as intermediaries between the clock signal source and the measurement instrumentation. These intermediary elements capture timing information directly at the chip level before signals leave the chip, acting as a buffer that prevents external noise and timing variations from corrupting the measurement. This mediator approach allows standard external equipment to be used while protecting measurement accuracy.
2Device complexity
If simulation is used to estimate clock jitter, then no additional hardware is required, but the measurement precision deteriorates due to difficulty in modeling mixed-signal and distributed sources of jitter
Solution Approach 1:
The invention enables the chip to perform its own jitter measurement using embedded launch and capture elements. The chip essentially measures itself by comparing timing of signals at different points within its own logic. This self-service approach eliminates the need for complex external simulation setups while providing actual measured data rather than modeled estimates, thereby improving precision without excessive hardware overhead.
Solution Approach 2:
The invention merges the jitter measurement functionality with the existing chip logic by using launch and capture elements that are integrated into the chip's synchronous data paths. Rather than adding completely separate measurement hardware, the measurement function is combined with the data path elements, reducing overall device complexity while enabling accurate direct measurement of jitter.
3Adaptability or versatility
If clock frequency is divided down for off-chip measurement, then the measurement can accommodate equipment limitations, but the measurement precision deteriorates due to additional frequency division jitter
Solution Approach 1:
The invention performs the timing measurement action before the clock signal leaves the chip, capturing launch and capture timestamps internally. By completing the critical measurement action prior to signal transmission through external frequency dividers and PCB traces, the measurement is immune to the jitter introduced by frequency division. This preliminary action approach allows equipment compatibility while preserving measurement accuracy.
Data Source
AI summary
Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.