On-Chip Clock Control for At-Speed Power Profile Testing
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Solution Overview
Problem
Existing semiconductor testing methods face challenges in achieving high toggle rates and power consumption due to limitations in the number of shift registers, leading to unsatisfactory current measurements and heat generation, and power droops that can cause devices to fail at-speed tests.
Innovation Solution
Implementing an on-chip clock controller (OCC) that controls clock speeds and pulse sequences to exceed the number of shift registers, allowing for increased toggle rates and power consumption by alternating between slow and fast clock pulses during shift-in and capture phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of shift registers is increased to achieve higher toggle rates, then the device complexity increases, but the manufacturing cost and device area increase proportionally
Solution Approach 1:
The patent implements dynamic clock frequency switching, where the clock controller alternates between first clock frequency (lower) and second clock frequency (higher) based on test requirements. This dynamic adjustment allows the system to achieve high toggle rates during capture phases without permanently increasing the number of shift registers, thereby resolving the contradiction between power/toggle rate and device complexity
Solution Approach 2:
The patent employs periodic alternation between different clock frequencies in a structured sequence: first clock frequency during shift-in phases, then second clock frequency during capture phases. This periodic action pattern enables the system to achieve high toggle rates intermittently for testing purposes while maintaining lower complexity architecture, effectively resolving the technical contradiction
2Power
If the clock speed is increased to achieve higher toggle rates, then the power consumption increases, but power droops occur causing test failures
Solution Approach 1:
The patent implements periodic alternation between low and high clock frequencies, where the high frequency (second clock frequency) is applied only during capture phases for the duration needed to achieve sufficient toggle rates, followed by transitions to low frequency during shift-in phases. This periodic action allows the system to achieve necessary power consumption levels for valid testing without sustaining high power draw that would cause droops and failures
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on the test phase requirements. During shift-in phases, the system operates at a first clock frequency that is lower than the second clock frequency used during capture phases. This parameter change allows the system to achieve high toggle rates only when necessary for testing, avoiding continuous high power consumption that would cause droops
3Power
If the number of capture pulses is increased to achieve sufficient toggle rates, then the test duration increases, but the productivity decreases
Solution Approach 1:
The patent changes the clock frequency parameter from a first clock frequency during shift-in phases to a second clock frequency (higher than the first) during capture phases. This parameter change enables the system to achieve sufficient toggle rates in fewer pulses during the critical capture phase, thereby maintaining test efficiency and productivity while meeting the minimum toggle rate requirements for valid power measurements
Data Source
AI summary
A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.