On-Chip Comparator Circuitry for Multi-Array Data Match Verification
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Solution Overview
Problem
Existing memory systems face challenges in accurately determining matches between data values stored across multiple arrays, which can lead to errors in data retrieval and execution of instructions, particularly in critical automated systems like autonomous vehicles, where reliable data integrity is crucial for safety and performance.
Innovation Solution
The implementation of comparator circuitry on a single memory chip to compare data values stored by multiple arrays, ensuring a match between at least two arrays, with an output component selecting and outputting data from one array based on the match, and a notification system for no match, enhancing data reliability and preventing potential errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data values are stored across multiple arrays for redundancy, then reliability is improved, but device complexity increases due to the need for comparator circuitry and match determination logic
Solution Approach 1:
The patent combines multiple memory arrays and their comparator circuitry into a single integrated memory device. The first and second memory arrays are formed on the same semiconductor substrate along with the comparator circuitry, merging what would traditionally be separate components into one unified device. This integration reduces overall system complexity while maintaining the reliability benefits of redundant storage and comparison.
Solution Approach 2:
The memory device performs self-verification by incorporating comparator circuitry that automatically compares data values between the first and second memory arrays. The device determines whether matching data values are stored in corresponding locations without requiring external verification systems, enabling the memory to service its own integrity checking needs and reducing the need for additional external complexity.
2Manufacturing precision
If comparator circuitry is integrated on the same chip as memory arrays, then manufacturing precision is improved, but area of stationary object increases
Solution Approach 1:
The patent merges the comparator circuitry with the memory arrays on a single semiconductor substrate, achieving precise integration through co-fabrication processes. This merging approach ensures accurate alignment and electrical connectivity between the memory arrays and comparator circuitry while optimizing the use of available chip area through shared substrate real estate.
Data Source
AI summary
Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.