On-Chip Data Block Sequencing for Reduced Latency
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Solution Overview
Problem
Conventional PCIe compliant interfaces and flit-based connections are inefficient for on-chip communication due to excessive overhead processing and inflexibility in data format, leading to latency and power consumption issues, especially in large SoC implementations.
Innovation Solution
The system divides payload data into multiple data blocks with corresponding error check blocks, allowing each block to be independently verified, even if the payload is incomplete, and transmits them over shared lines, using error checks like parity bits or CRC, to enable efficient and flexible data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PCIe compliant interfaces use multiple communication layers for broad usability, then adaptability is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent segments the payload into multiple data blocks, each with its own error check block. This allows independent verification and processing of individual blocks, reducing the complexity of verifying entire payloads and enabling parallel processing, thus lowering processing overhead while maintaining adaptability.
Solution Approach 2:
Error check blocks are generated and attached to each data block before transmission. This preliminary action enables receivers to verify data integrity immediately upon receiving each block without waiting for the complete payload, reducing processing delays and overhead.
2Reliability
If conventional PCIe interfaces process data through multiple layers, then reliability is improved, but latency increases
Solution Approach 1:
By dividing the payload into separate data blocks with individual error check blocks, the system enables parallel verification of multiple blocks. This segmentation reduces the time required to verify data integrity compared to processing the entire payload sequentially, thus reducing latency while maintaining reliability.
Solution Approach 2:
Error check blocks are prepared in advance and attached to each data block before transmission. This allows receivers to perform integrity checks immediately upon receiving each block without waiting for the complete payload or undergoing multiple layer processing, significantly reducing latency while ensuring reliability.
3Ease of manufacture
If PCIe messages use fixed formats for protocol compliance, then standardization is improved, but adaptability for different data formats decreases
Solution Approach 1:
The patent segments payloads into variable-sized data blocks that can accommodate different data formats and sizes. Each block is independently processed and verified, allowing the system to handle diverse data types (flags, bit counters, etc.) while maintaining protocol compliance through standardized error checking mechanisms.
Solution Approach 2:
The system dynamically adjusts the number and size of data blocks based on the specific payload requirements. This dynamic segmentation allows the same protocol framework to adapt to various data formats and sizes, providing both standardization and flexibility.
4Speed
If flit-based connections are used for on-chip communication, then communication speed is improved, but overhead processing increases
Solution Approach 1:
By segmenting the payload into data blocks with individual error check blocks, the system enables efficient parallel processing and verification. This reduces the overhead associated with flit-based communication by allowing independent handling of multiple blocks, thereby reducing energy consumption for overhead processing while maintaining high communication speed.
Data Source
AI summary
The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.