On-Chip Data Folding for Non-Volatile Memory Endurance
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Solution Overview
Problem
Current flash memory systems face inefficiencies in data management, particularly in updating data within large erase blocks, leading to frequent garbage collection and premature memory aging due to inefficient handling of sequential and chaotic update patterns, and lack a systematic approach for high-capacity, high-performance non-volatile memory operations.
Innovation Solution
A method for operating a non-volatile memory system that includes a controller circuit and memory circuit with arrays of non-volatile memory cells, where data is written in binary format pages and then folded into a multi-state format through N-state per cell programming operations, balancing performance across allocation units and using a list of free blocks to optimize block selection for writing data, thereby improving uniformity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written into large erase blocks, then storage capacity is improved, but garbage collection frequency increases and memory endurance deteriorates
Solution Approach 1:
The patent divides the memory array into multiple independently controllable memory arrays (e.g., first memory array, second memory array, third memory array) that can be managed separately. This segmentation allows the system to perform garbage collection on specific arrays without affecting the entire memory space, thereby reducing the impact on memory endurance while maintaining high storage capacity through the use of multiple arrays.
Solution Approach 2:
The patent implements a background process that proactively performs garbage collection and balance operations before data writes complete. The controller monitors write operations and initiates background garbage collection to maintain a balanced state across memory arrays, preventing premature aging and extending memory endurance while supporting large block storage.
2Productivity
If sequential update operations are performed, then data management efficiency is improved, but garbage collection frequency increases
Solution Approach 1:
The patent dynamically adjusts the balance between sequential and chaotic update operations based on real-time monitoring of memory array states. The controller adapts the update pattern to maintain balance across memory arrays, performing garbage collection only when necessary to maintain optimal performance, thereby reducing garbage collection frequency while preserving data management efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where the controller continuously monitors the state of multiple memory arrays and adjusts garbage collection operations accordingly. By monitoring array balance and only initiating garbage collection when imbalance thresholds are exceeded, the system reduces unnecessary garbage collection frequency while maintaining data management efficiency.
3Quantity of substance
If N-state per cell programming operations are used, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the programming operation into distinct phases (first phase, second phase, third phase) where each phase targets specific memory arrays or data portions. This segmentation allows the system to perform N-state programming in manageable steps with controlled precision requirements, reducing the overall manufacturing precision burden while maintaining high storage density through multi-state encoding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of data management by reducing garbage collection frequency, improving memory endurance, and enabling high-capacity, high-performance operations by optimizing data handling and block management within the flash memory system.
Implementation Method 1
performing a N-state per cell programming operation of the N pages from the registers into a second section of the array, wherein the N-state per cell programming operations a first phase and a second phase
Implementation Method 2
The data written in binary format pages is folded into the array in a multi-state format
Data Source
AI summary
A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations. When the memory system needs a memory block for the writing of data, it selects blocks from a free block list, where the free block list includes a reserve portion that is only accessible for a specified set of commands.