On-Chip Data Lock Detection in High-Speed Serial Links
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Solution Overview
Problem
Existing methods for measuring data lock time in high-speed serial data links are inaccurate and prone to false indications, particularly due to oversampling and reliance on external equipment like BERTs and 8B/10B decoders, which are time-consuming and limited in their accuracy and applicability.
Innovation Solution
An on-chip method involving programmable data pattern registers and a byte detection state machine to filter false indications and accurately measure data lock time by comparing incoming data streams to a searchable pattern, allowing for efficient detection and measurement of data lock within high-speed serial data links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If 2× oversampling is used to save power, then power consumption is reduced, but data lock detection accuracy deteriorates causing false lock indications
Solution Approach 1:
The patent implements preliminary actions by maintaining a reference pattern of expected data bits and proactively comparing incoming data against this reference before making lock determination. The system prepares the reference pattern in advance and uses it to predict what valid data should look like, enabling accurate lock detection even at 2× oversampling rates without false indications.
2Difficulty of detecting and measuring
If external equipment like BERT is used to measure data lock time, then measurement capability is provided, but measurement accuracy deteriorates due to equipment lock time swamping the actual lock time delay
Solution Approach 1:
The patent extracts the data lock detection and measurement functionality from external equipment and implements it directly within the receiver chip. By taking out the measurement capability from external BERT equipment and integrating pattern comparison logic into the receiver itself, the system eliminates the external equipment's lock time from the measurement, achieving accurate measurement of the actual data lock time delay.
Solution Approach 2:
The receiver performs self-service by autonomously detecting and measuring its own data lock time using internal pattern comparison resources. The system uses its own logic resources to generate reference patterns and compare incoming data, eliminating the need for external measurement equipment and their associated delays.
3Measurement precision
If 8B/10B decoders are used to approximate lock time measurement, then lock time can be approximated, but measurement accuracy deteriorates and the method is limited to valid 8B/10B coding
Solution Approach 1:
The patent implements a universal pattern comparison mechanism that can detect any arbitrary bit pattern, not just 8B/10B encoded bytes. The reference pattern can be programmed to match any expected data sequence, making the lock detection method applicable to multiple encoding domains and protocols without requiring specific decoder hardware, thereby achieving both accuracy and versatility.
4Adaptability or versatility
If multiplexing is used to switch between serial input streams for lock time measurement, then lock time can be measured between different sources, but device complexity increases
Solution Approach 1:
The patent uses a programmable pattern register as an intermediary to store the reference pattern, which mediates between the incoming data stream and the comparison logic. This intermediary structure enables flexible pattern matching without requiring complex multiplexing circuits, as the reference pattern can be reprogrammed to represent different data sources or encoding schemes, simplifying the overall measurement system while maintaining multi-source capability.
Data Source
AI summary
A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.