On-Chip Delay Circuits for Memory Skew Compensation
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Solution Overview
Problem
The existing solutions for addressing skew in a byte lane, caused by connectors with internal conductors of different lengths, require adjustments to the mother board trace lengths, which are not universal and can be inconvenient, especially when using different types of connectors.
Innovation Solution
Implementing on-chip delay circuits in the memory module to compensate for skew by intentionally delaying some output signals, allowing for programmable adjustments to accommodate various connector configurations and environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trace length adjustments are made on the mother board to compensate for skew, then data timing alignment is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The skew compensation function is extracted from the mother board and relocated to the memory module itself through on-chip delay circuits. This removes the need for complex trace length adjustments on the mother board while maintaining data timing alignment.
Solution Approach 2:
On-chip delay circuits are introduced as intermediary elements within the memory module to compensate for conductor length differences. These delay circuits act as mediators that adjust signal timing without requiring changes to the mother board trace configuration.
2Manufacturing precision
If fixed trace length adjustments are implemented, then skew compensation is achieved for a specific connector type, but adaptability to different connector configurations is reduced
Solution Approach 1:
The delay circuit configuration is made programmable and adjustable, allowing the memory module to adapt to different connector types and conductor length variations. This dynamic configuration capability enables the same module to work with various connector configurations without requiring custom trace adjustments for each type.
Solution Approach 2:
The memory module design incorporates universal delay compensation capabilities that can accommodate multiple connector types. The programmable delay circuits provide multi-functional skew compensation that works across different connector configurations, eliminating the need for connector-specific mother board designs.
3Adaptability or versatility
If on-chip delay circuits are added to the memory module, then skew compensation becomes universal and programmable, but device complexity within the module increases
Solution Approach 1:
The memory module performs self-adjustment of signal timing through programmable delay circuits that can be configured based on the specific connector and application requirements. This self-service capability allows the module to automatically compensate for skew without requiring external intervention or complex external circuitry.
Data Source
AI summary
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.