On-Chip Droop Switch for Power Domain Supply Drooping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing System on Chip (SoC) devices employing 28 nm semiconductor features face limitations in automatic dynamic voltage scaling, as flip-flop designs retain state at lower voltages than the scaled voltage range, leading to potential leakage current savings that are not fully realized due to the inability to lower voltages below the typical automatic DVS range.
Innovation Solution
A power supply system that enables a low-effort retention mode by using separate voltage regulators to provide a second, lower voltage sufficient for flip-flops to retain their state, achieved through a droop circuit that reduces the voltage by a diode forward bias drop, allowing for efficient power management and state retention without guaranteeing logic operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the voltage is scaled down to the minimum AVS range (0.72V), then power consumption is reduced, but flip-flops cannot retain their state and leakage current savings are lost
Solution Approach 1:
The power supply is segmented into two separate voltage domains: a first voltage domain (e.g., 0.72V-1.0V) for logic operation and a second voltage domain (e.g., 0.4V-0.6V) for state retention. This allows different voltage levels to coexist, enabling flip-flops to retain state at lower voltages without affecting logic functionality, thus reducing power consumption while maintaining reliability.
Solution Approach 2:
A droop circuit is introduced as an intermediary component between the voltage regulator and the flip-flops. This droop circuit generates the second lower voltage from the first voltage by utilizing the forward voltage drop of a diode-connected transistor, enabling voltage transformation without requiring an additional voltage regulator, thus achieving state retention at lower voltage while simplifying the power supply architecture.
2Reliability
If a second voltage regulator is added to provide lower retention voltage, then state retention at lower voltage is achieved, but device complexity increases
Solution Approach 1:
The droop circuit is designed to be a multi-functional component that serves both as a voltage transformation element and as a power distribution element. By using a diode-connected transistor configuration, the same circuit structure can generate the voltage drop needed for retention mode while also providing the necessary current drive capability, thus achieving multiple functions without adding separate dedicated circuits for each function.
Solution Approach 2:
The droop circuit utilizes the inherent forward voltage drop characteristic of the diode-connected transistor to automatically generate the second lower voltage from the first voltage. This self-regulating mechanism eliminates the need for external control circuits or additional regulation stages, as the voltage transformation occurs naturally through the physical property of the transistor, thereby reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and accelerates recovery from low-power states, offering a scalable and efficient intermediate power level with faster recovery times compared to traditional clock gating and power gating methods, while minimizing the need for additional power supplies and specialized cell designs.
Implementation Method 1
The second voltage can be produced by a voltage drop (droop) from the first voltage. The preferred embodiment includes a System On Chip and two external voltage regulators or one external voltage regulators and an on-chip droop circuit for each circuit module.
Data Source
AI summary
This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.