On-Chip Electromigration Sensor for Semiconductor Reliability
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Solution Overview
Problem
Existing methods for monitoring electromigration in semiconductor chips are inadequate as they fail to accurately represent real-life conditions and do not effectively detect failures during the chip's useful lifetime, leading to unpredictable system crashes.
Innovation Solution
An on-chip EM sensor that compares a variable voltage drop across a monitored conductive interconnect with a reference voltage to detect when the resistance exceeds a threshold, allowing for timely replacement or voltage reduction to prevent failure, using a resistive voltage divider circuit and comparators to determine the resistance value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dummy metal features are used for EM testing at wafer-level, then chip screening efficiency is improved, but the monitoring capability during the chip's useful lifetime is lost
Solution Approach 1:
The monitoring function is segmented from the traditional wafer-level test structure and integrated directly into the chip's operational circuitry. The conductive interconnect is divided into a monitored portion with embedded sensing capability, allowing continuous monitoring during the chip's useful lifetime rather than only at wafer-level testing.
Solution Approach 2:
The monitoring structure is built into the chip during manufacturing with preliminary calibration of threshold values. This preliminary action enables the chip to autonomously monitor its own degradation and trigger warnings before failure occurs, eliminating the need for separate post-packaging testing.
2Speed
If accelerated stress testing is applied to dummy features, then failure detection speed is improved, but the accuracy of representing real-life EM conditions deteriorates
Solution Approach 1:
The monitoring structure replicates the local quality and topology of actual conductive interconnects including corners and via contact regions, rather than using simplified dummy features. This local fidelity ensures that the EM degradation experienced by the monitored interconnect accurately represents real-life conditions while maintaining continuous monitoring capability.
Solution Approach 2:
Instead of using dummy features that poorly copy real interconnects, the invention creates an accurate copy of the actual conductive interconnect topology within the operational circuit. The monitored interconnect is a true representation of the critical paths, ensuring that degradation patterns match real-life EM failure mechanisms.
3Duration of action of stationary object
If on-chip monitoring is implemented, then continuous detection during useful lifetime is achieved, but device complexity increases
Solution Approach 1:
The monitored conductive interconnect serves multiple functions: it is both a functional circuit element and a monitoring structure. The same interconnect that carries operational current also provides the resistance measurement for EM degradation detection, eliminating the need for separate dedicated monitoring structures and reducing overall device complexity.
Solution Approach 2:
The chip performs self-monitoring of its own EM degradation through the integrated detection circuit that measures resistance changes in its operational interconnects. This self-service capability eliminates the need for external monitoring equipment or complex additional sensing structures, achieving continuous monitoring with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables continuous monitoring of semiconductor chip degradation due to electromigration, allowing for proactive replacement or performance adjustments to extend chip lifetime and prevent system crashes.
Implementation Method 1
compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip so as to detect when the resistance of the monitored element is over threshold
Implementation Method 2
A resistive voltage divider circuit in the semiconductor chip is operable to output a plurality of reference voltages ranging from a first voltage to a second voltage
Implementation Method 3
A plurality of comparators are provided in the semiconductor chip, each of which has a first input and a second input. The first input is coupled to receive one of the plurality of reference voltages output by the resistive voltage divider circuit and the second input is coupled to receive a monitored voltage representative of a resistance of the monitored element
Implementation Method 4
Electromigration tends to produce voids within metal conductors) due to movement of metal ions in directions parallel to high density current flow within the chip
Implementation Method 5
When EM occurs within the dummy feature, local joule heating therein causes carrier mobility within the EM sensor to increase drastically
Data Source
AI summary
A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.